Who this is aimed at

This is written for UK job seekers aiming at roles such as:

• Semiconductor Process Engineer, Device Engineer, Integration Engineer

• Yield Engineer, Defect Engineer, Metrology Engineer

• Test Engineer, Product Engineer, Reliability Engineer

• Analogue IC Engineer, RF Engineer, Mixed Signal Engineer

• Digital Design Engineer, Verification Engineer, EDA Engineer

• Applications Engineer, Field Engineer, Failure Analysis Engineer

Same maths topics apply. Your emphasis changes by track:

• Device & process lean harder on electrostatics, transport, exponentials, fitting

• IC design & RF lean harder on complex numbers, frequency response, noise

• Yield, quality & manufacturing lean harder on statistics, SPC, DOE, yield models

What employers really mean by “strong maths”

In semiconductor interviews, “maths” usually means you can do three things:

1. Translate physical behaviour into a simple model

2. Sanity check magnitudes & units quickly

3. Use statistics to separate real shifts from noise

You rarely need proofs. You need fluency with the shapes of equations & what they imply.

The only maths topics you actually need

1) Exponents & logs: the language of semiconductor behaviour

Semiconductor behaviour is full of exponential relationships. If you get comfortable with exponentials & logs, a lot of “device mystery” becomes readable.

What you actually need

• log rules in practice (log of product, log of ratio)

• straight-line thinking on log plots

• temperature dependence intuition

• “order of magnitude” comfort

Where it shows up

• diode & transistor current behaviour

• leakage & subthreshold

• Arrhenius plots for temperature acceleration in reliability

• parameter extraction from measured curves

MIT’s microelectronic devices lecture materials explicitly develop exponential relationships in the context of semiconductor equations & modelling which is a useful anchor for what you are trying to learn. MIT OpenCourseWare

Mini exercise
Take any measured current vs voltage curve, plot it on linear axes then semi-log axes. Write 8–10 lines explaining what becomes clearer on the log plot.

2) Calculus intuition: rates, slopes & “how fast things change”

You do not need heavy calculus for most semiconductor roles. You do need to be comfortable with:

• a derivative as a rate of change

• a gradient as “change across distance”

• an integral as “accumulated amount”

• differential equations as “rules for how things evolve”

This matters because device physics is often framed through equations that connect potential, charge, field & carrier concentration.

Where it shows up

• electrostatics in junctions & MOS structures

• transport models

• extracting parameters from curves by looking at slopes

MIT’s p-n junction electrostatics lecture explicitly uses Poisson’s equation to connect electrostatic potential with charge distribution. MIT OpenCourseWare

Mini exercise
Pick one plotted curve you see often in semiconductors (Id–Vg, Id–Vd, leakage vs T). Write what the slope means physically in one operating region.

3) Device electrostatics & transport basics you actually use

You do not need to solve full device PDEs by hand. You do need the core mental model.

A) Poisson equation intuition

Poisson’s equation is the backbone link between charge & electrostatic potential in semiconductor regions such as a depletion region. MIT’s lecture notes frame Poisson’s equation in the p-n junction electrostatics context. MIT OpenCourseWare

What you need to know

• what the equation is connecting (charge ↔ potential)

• why depletion approximations exist

• why doping profiles shape fields & potentials

B) Drift & diffusion intuition

Carrier transport is usually introduced through drift current (field-driven) & diffusion current (concentration-gradient-driven). MIT’s integrated microelectronic devices materials explicitly list drift & diffusion topics as a core lecture block. MIT OpenCourseWare

What you need to know

• drift increases with electric field

• diffusion increases with concentration gradient

• why both exist simultaneously

• why “mobility” is a key parameter

C) Quasi-Fermi level awareness

Once you see “quasi-Fermi levels” in device discussions, the only thing you need early on is the concept: under non-equilibrium, electron & hole populations can be described with separate quasi-Fermi levels. NPTEL’s semiconductor device materials include PN junction equilibrium framing with Fermi level discussion. NPTEL

Mini exercise
Write a one page note titled “What sets the electric field in a junction” using only plain English plus one sketch.

4) MOSFET maths you actually need for most roles

MOSFETs dominate modern ICs. Most job seekers overcomplicate this.

What you actually need

• operating regions in plain English (off, linear, saturation)

• threshold voltage as a practical concept

• why subthreshold matters

• “gradual channel” model intuition for current behaviour

MIT OCW includes detailed MOSFET lecture notes including I–V characteristics & large signal modelling plus drain current modelling notes. MIT OpenCourseWare
MIT also provides a dedicated lecture on subthreshold MOSFET operation which is especially relevant for low power work. MIT OpenCourseWare

Where it shows up

• low power design trade-offs

• leakage analysis

• process corner discussions

• parameter extraction from measurements

• reliability effects (Vt shift, mobility degradation)

Mini exercise
Build a simple spreadsheet or notebook that models Id in linear & saturation regions using a basic long channel approximation. Then write “What breaks first in real silicon” as bullet points.

5) Complex numbers for AC, analogue & RF

If you are aiming at analogue, mixed signal, RF, high speed IO or power, complex numbers stop being optional.

What you actually need

• j as √(-1) & what it represents in sinusoidal steady state

• impedance as a complex quantity

• phasors for voltages & currents

• magnitude & phase interpretation

Where it shows up

• frequency response, poles & zeros in practice

• matching networks

• stability discussions at a high level

• filter behaviour & bandwidth

You do not need to memorise every derivation. You need to be able to look at a transfer function plot & explain what changes when a pole moves.

6) Signals maths: bandwidth, Fourier intuition & noise

A lot of semiconductor work comes down to: “What bandwidth do we care about” plus “What is the noise floor” plus “How does that impact performance”.

What you actually need

• bandwidth as a practical limiter

• noise power density language

• kTB thermal noise awareness

• shot noise as a concept in junction devices

Texas Instruments’ noise figure analysis note explicitly references thermal noise power concepts including kTB framing in the context of noise figure workflows. Texas Instruments
For shot noise intuition in semiconductor junction devices, Analog Devices discusses shot noise generation in active devices where charge crosses a potential barrier such as diodes & transistors. Analog Devices

Where it shows up

• ADC front ends

• RF receiver chains

• sensor interfaces

• PLL jitter conversations

• test limits & guard bands

Mini exercise
Take a simple amplifier chain. Estimate the thermal noise floor for a bandwidth. Then write what you would change first to improve SNR.

7) Statistics that actually gets you hired in manufacturing roles

If you want process, yield, quality, metrology, product engineering or reliability, statistics is the maths that matters most.

A) SPC basics

You should understand control charts at a practical level.

NIST’s Engineering Statistics Handbook provides clear guidance on Shewhart X-bar & R charts including how they relate to process variability. itl.nist.gov
SEMI also frames SPC as a central quality management tool for predictable quality in manufacturing contexts. semi.org

What you actually need

• mean & standard deviation

• control limits vs spec limits

• common cause vs special cause thinking

• capability basics (Cp, Cpk) at an intuition level

B) DOE basics

Design of experiments is a career accelerant in semiconductor process work because it helps you learn faster with fewer wafers.

NIST’s DOE guidance explains two-level full factorial designs & provides worked examples. itl.nist.gov

What you actually need

• factors, levels, responses

• interaction awareness

• why randomisation matters

• how to interpret main effects plots

C) Yield models

Yield is often modelled with Poisson-style defect assumptions in a first pass.

A lecture note on yield modelling describes the Poisson die yield model & shows how defect density relates to observed die yield. fog.misty.com
If you want a broader overview of yield model development beyond simple Poisson, there is also academic literature reviewing Poisson mixture approaches. ScienceDirect

What you actually need

• why yield drops with die area

• defect density intuition

• why clustering breaks simple assumptions

Mini exercise
Build a small yield calculator using the Poisson model. Then write a paragraph titled “When this model lies” referencing defect clustering.

8) Basic optimisation habits for every track

Semiconductor work is optimisation under constraints: performance, power, area, yield, cost, schedule, reliability.

You do not need an optimisation theory course. You do need the habits:

• fit a simple model to data

• validate the model with held-out points

• quantify trade-offs

• avoid overfitting your conclusions to one wafer lot

A 6 week maths plan for semiconductor job readiness

Aim for 4–5 sessions per week of 30–60 minutes. Each week produces a portfolio output.

Week 1: Exponentials, logs & curve reading

Learn

• log transforms

• slope meaning on semi-log plots
  Build

• a notebook that imports a curve dataset, plots linear & semi-log, extracts slope in one region
  Output

• repo: semiconductor-curves-log-plots

Anchor learning with MIT device modelling notes that develop exponential behaviour in semiconductor contexts. MIT OpenCourseWare

Week 2: Junction electrostatics intuition

Learn

• depletion approximation idea

• what Poisson equation is connecting
  Build

• a simple depletion width calculator under basic assumptions

• a short explanation page with sketches
  Output

• repo: pn-junction-electrostatics

Use MIT p-n junction electrostatics lecture as your reference anchor. MIT OpenCourseWare

Week 3: MOSFET I–V behaviour & regions

Learn

• off, linear, saturation

• threshold & subthreshold intuition
  Build

• a long channel Id model notebook

• compare predicted curves vs a sample dataset or a simulated dataset
  Output

• repo: mosfet-iv-basics

MIT MOSFET I–V lecture notes plus drain current modelling notes are ideal anchors. MIT OpenCourseWare

Week 4: Noise, bandwidth & complex numbers basics

Learn

• impedance & phasors

• bandwidth & noise density language
  Build

• a simple AC response calculator for an RC low pass

• a noise floor estimate for a bandwidth using kTB framing
  Output

• repo: ac-noise-basics

Use TI’s noise figure analysis note as a reference for thermal noise framing in system calculations. Texas Instruments

Week 5: SPC for semiconductor manufacturing

Learn

• control charts, control limits, signals vs noise
  Build

• generate a control chart from a sample dataset

• label points as in-control vs out-of-control with explanations
  Output

• repo: semiconductor-spc-control-charts

Use NIST control chart guidance as your anchor reference. itl.nist.gov

Week 6: DOE or yield capstone depending on your target

Pick one path:

Path A: Process engineer style DOE

• run a factorial design on a toy process model

• estimate main effects & interactions

• write a recommendation note
  NIST’s factorial design pages provide a clear starting point. itl.nist.gov

Path B: Yield engineer style yield modelling

• implement Poisson die yield model

• add a simple clustered defect scenario discussion

• write “what data I would request next”
  Use the yield modelling lecture note as an anchor. fog.misty.com

Portfolio projects that prove the maths to semiconductor employers

Project 1: MOSFET curve extraction notebook

What you deliver

• Id–Vg curve plots

• extracted threshold estimate using a chosen method

• short discussion on subthreshold slope & leakage relevance
  Anchor: MIT MOSFET lecture notes. MIT OpenCourseWare

Project 2: Junction electrostatics explainer

What you deliver

• a one page visual explainer

• a depletion width calculator under assumptions
  Anchor: MIT p-n junction electrostatics lecture. MIT OpenCourseWare

Project 3: Noise budgeting mini report

What you deliver

• bandwidth definition

• thermal noise floor estimate

• one improvement path with trade-offs
  Anchor: TI noise figure analysis note. Texas Instruments

Project 4: SPC control chart pack

What you deliver

• X-bar & R charts for a process metric

• explanation of signals that indicate special cause variation
  Anchor: NIST control chart guidance. itl.nist.gov

Project 5: DOE mini study

What you deliver

• a two-level factorial plan

• results analysis with main effects & interactions

• a recommendation memo
  Anchor: NIST factorial design guidance. itl.nist.gov

Project 6: Yield model calculator

What you deliver

• Poisson die yield calculator

• discussion of assumptions

• what real fab data you would want next
  Anchor: yield modelling lecture note on Poisson die yield. fog.misty.com

How to write this on your CV

Avoid “strong maths” as a claim. Use proof like:

• Built MOSFET I–V modelling notebook plus parameter extraction notes aligned to standard device modelling concepts MIT OpenCourseWare

• Produced a p-n junction electrostatics explainer using Poisson equation intuition plus depletion approximation assumptions MIT OpenCourseWare

• Estimated noise floor & bandwidth trade-offs using thermal noise framing used in noise figure workflows Texas Instruments

• Implemented SPC control charts using recognised Shewhart X-bar & R chart structure to separate process drift from noise itl.nist.gov

• Designed a two-level full factorial DOE plan to quantify main effects & interactions with structured analysis itl.nist.gov

• Built a Poisson die yield calculator linking defect density assumptions to expected die yield fog.misty.com

Resources section

Device physics & MOSFET foundations

• MIT OCW 6.012 Microelectronic Devices & Circuits lecture notes hub. MIT OpenCourseWare

• MIT OCW p-n junction electrostatics lecture PDF. MIT OpenCourseWare

• MIT OCW MOSFET I–V characteristics lecture PDF. MIT OpenCourseWare

• MIT OCW MOSFET drain current modelling notes. MIT OpenCourseWare

• MIT OCW subthreshold MOSFET operation lecture. MIT OpenCourseWare

• MIT OCW Integrated Microelectronic Devices lecture notes listing drift & diffusion topics. MIT OpenCourseWare

• NPTEL PN junction module for Fermi level equilibrium intuition. NPTEL

Semiconductor manufacturing, process control, yield

• Leachman yield modelling notes covering Poisson die yield model & defect density relationship. fog.misty.com

• Review paper on yield model development using Poisson mixture approaches. ScienceDirect

• Fundamentals of Semiconductor Manufacturing & Process Control book PDF (May & Spanos). gacbe.ac.in

• SEMI commentary on SPC as a central quality management tool. semi.org

SPC & DOE practical references

• NIST Engineering Statistics Handbook: Shewhart X-bar & R charts. itl.nist.gov

• NIST Engineering Statistics Handbook: two-level full factorial designs. itl.nist.gov

Noise & signal chain basics

• Texas Instruments: Signal Chain Noise Figure Analysis including thermal noise framing. Texas Instruments

• Analog Devices: shot noise discussion in active semiconductor devices. Analog Devices