Latest UK roles, updated daily.
This role involves designing and integrating analog/mixed-signal circuits for advanced semiconductor packaging and heterogeneous integration. Responsibilities include PHY-level interfaces, custom pad circuits, and working with industry partners to develop and commercialize innovative solutions.
This role involves leading the validation and characterisation of analogue and mixed-signal ASICs for trapped-ion quantum processors. Responsibilities include test planning, platform development, first-silicon bring-up, and system integration, with a focus on cryogenic testing and reusable automation.
Design GaN power ICs and Si gate drivers using EDA tools, covering schematic capture, RTL, analog/digital and mixed-signal simulation, synthesis, STA, PNR and AMS verification. Also develops test solutions, analyses wafer-level and packaged device data, documents designs, debugs ICs and generates IP for patent applications within a growing R&D engineering team.
Senior leadership role owning the packaging function for GaN power semiconductors, combining people leadership with hands-on design of wirebond, flip chip and embedded packages. Involves multiphysics simulation, supplier development, qualification testing and roadmap input, working with internal teams and overseas partners from the Cambridge office.
Integrate all features needed to operate quantum computers into complex multi-layer ion-trapping chips, guiding designs from requirements through layout and tape-out. Work closely with scientists and fabrication engineers on metal-track routing and photonics/CMOS interfaces, using GDSFactory in Python and Cadence. Hybrid role, three days per week in the Oxford office.
Owns the full FPGA development lifecycle on a defence and aerospace programme, from requirements capture and architecture through VHDL implementation, verification and integration onto target hardware. Also leads and mentors other engineers, manages work packages to cost and quality targets, and reports progress to engineering leadership. Based fully on-site in Newport under SC clearance.
Develops novel FPGA firmware for advanced defence technologies, working across the full project lifecycle from concept through design and development to customer handover. Projects span DSP, radar and SDR domains using VHDL or Verilog with Vivado or Quartus, alongside top-tier scientists and engineers in a collaborative multidisciplinary team.
Develops and validates predictive models of source-gated and multimodal transistors on an EPSRC project, using TCAD, compact modelling, surrogate modelling or physics-informed machine learning. Works closely with experimental researchers to fit models against measured data and inform device and circuit design, producing publications and reusable simulation frameworks.
Design, develop and verify FPGA solutions in VHDL across the full development lifecycle, from requirements capture and architecture definition to simulation, validation and hardware integration. You'll provide technical leadership within a multidisciplinary team on a Defence & Aerospace programme, using Xilinx, Altera or Microsemi devices with Vivado, Quartus II, ModelSim or Libero tooling.
Join a multidisciplinary team building integrated software-hardware systems for defence and security, spanning low-power embedded devices to high-throughput server applications. You'll apply C/C++, FPGA, and electronics skills to complex projects combining custom hardware with innovative software, with labs and prototyping facilities on site.
Provides technical leadership for a global EDA/CAD compute and engineering infrastructure, spanning Linux environments, LSF batch compute, EDA license servers, Perforce and project/workspace provisioning. Combines hands-on Python and shell automation with architecture, monitoring and capacity planning, working across engineering, CAD and IT/IS teams to keep semiconductor development environments consistent and reliable worldwide.
Provides technical leadership for a global EDA/CAD compute and engineering infrastructure, spanning Linux environments, LSF batch compute, EDA license servers, Perforce and project/workspace provisioning. Combines hands-on engineering with architecture and operational ownership, building Python and shell automation, monitoring dashboards and capacity planning. Works across engineering, CAD and IT/IS teams to keep environments scalable and globally consistent for semiconductor development.
Owns dense, high-layer-count PCB layout from schematic handoff to fabrication release, covering stackups, HDI structures, controlled-impedance routing, differential pairs and BGA breakout for large FPGAs and custom ASICs. Acts as the main technical contact with fabricators and assembly houses, and sets the footprint libraries, design rules and CAD standards the wider team works to.
Owns signal and power integrity across high-speed boards and packages, running pre-layout channel studies, post-layout SI analysis with IBIS-AMI models, and PDN impedance and DC drop work for high-current ASIC and FPGA rails. Channels span chip, package, interposer, board and optical engine, with heavy bench correlation using VNAs, TDRs and oscilloscopes to feed design rules.
Hands-on precision production and testing of small, high-tolerance electro-optic and electronic components in an Aerospace & Defence facility. Work includes micro-assembly with hand tools, microscopes and fixtures, inspection, and following detailed drawings and quality standards, with some roles in cleanroom or controlled-temperature areas.
