Latest UK roles, updated daily.
This role involves designing and integrating analog/mixed-signal circuits for advanced semiconductor packaging and heterogeneous integration. Responsibilities include PHY-level interfaces, custom pad circuits, and working with industry partners to develop and commercialize innovative solutions.
This role involves leading the validation and characterisation of analogue and mixed-signal ASICs for trapped-ion quantum processors. Responsibilities include test planning, platform development, first-silicon bring-up, and system integration, with a focus on cryogenic testing and reusable automation.
The Senior QPU Design Engineer will integrate features into complex chips for quantum computers, collaborating with scientists and fabrication engineers. Responsibilities include chip layout, multi-layer design, and project ownership.
Lead the development and execution of manufacturing test strategies for an advanced AI accelerator chip, overseeing both internal teams and external partners. Drive test architecture, DFT integration, and silicon bring-up across high-speed interfaces like PCIe Gen6 and LPDDR, with a focus on yield, scalability, and advanced packaging. Work closely with cross-functional teams to ensure robust test coverage and successful high-volume manufacturing transfer.
Develop and debug ATE test programs for an advanced AI accelerator chip, covering digital logic, memory, and high-speed interfaces. Perform silicon bring-up, characterization, and failure analysis while collaborating with design and DFT teams. Support high-volume manufacturing ramp and advanced packaging test flows.
The role involves designing and developing GaN power ICs and Si gate drivers, using EDA tools for schematic capture, simulations, and verification. Responsibilities include testing, data analysis, and generating IP for patent applications, contributing to the company's R&D efforts in energy-efficient power electronics.
Leads the development of advanced semiconductor packaging solutions for GaN power devices, combining technical expertise with strategic leadership. The role involves hands-on design, multiphysics simulation, and cross-functional collaboration to deliver high-performance, energy-efficient packages. Focuses on innovation in thermal, electrical, and mechanical performance while shaping the future technology roadmap.
The Senior FPGA Engineer will work on advanced FPGA solutions for cutting-edge Defence and Aerospace projects, from requirements capture to integration. Responsibilities include architectural design, verification, and leading a team of FPGA engineers in a secure, mission-critical environment.
This role involves advanced semiconductor device modelling and simulation, focusing on source-gated transistors (SGTs) and multimodal transistors (MMTs). The researcher will develop and validate predictive models using TCAD, compact modelling, and AI-assisted techniques, working closely with experimental teams and contributing to high-quality research outputs.
This role involves developing novel FPGA designs for defence projects, working on a wide range of projects from initial concepts to final product handover. You will collaborate with a team of top-tier scientists and engineers, focusing on protecting Britain from its adversaries.
This role involves building integrated software-hardware systems for defence and security applications, ranging from low-power embedded systems to high-throughput server applications. You will join a multidisciplinary team of scientists and engineers, working on complex and innovative projects that combine custom hardware and software.
This role involves laying out complex, high-layer-count PCBs for an innovative optical computing system. Responsibilities include controlled-impedance routing, BGA breakout, and managing the entire manufacturing process from schematic to fabrication release.
This role involves owning signal and power integrity across high-speed PCB designs, from pre-layout channel studies to post-layout analysis, material evaluation, and simulation correlation. The engineer will work closely with the ASIC team to ensure end-to-end channel and power integrity, and develop reusable design guidelines and model libraries.
Design and optimize FPGA-based systems for ultra-low-latency, high-throughput data processing in custom hardware acceleration and performance-critical infrastructure. Work on both simple circuitry and complex technical challenges in a collaborative, innovation-driven team environment. Focus on timing closure, digital design, and hardware/software co-design for cutting-edge hardware systems.
This role involves providing technical leadership for Renesas' global engineering compute and design-data-management environment. Responsibilities include managing compute infrastructure, Perforce/IPLM-based design data management, project and workspace methodologies, automation, and supporting engineering teams. The role requires significant experience in EDA/CAD engineering, strong Linux/Unix knowledge, and expertise in Perforce Helix and semiconductor EDA workflows.
