Semiconductor Jobs

Senior Analog / Mixed-Signal Design Engineer

Designs PHY-level and die-to-die interfaces, custom pad circuits, drivers, receivers, ESD structures, termination and clocking for heterogeneous integration demonstrators. Handles floorplanning, I/O ring planning and interface layout across dies, interposers and packaging substrates, and acts as Technical Authority for analog/mixed-signal interfaces while supporting industry partners and workshops.

University of Southampton Southampton £46,049 – £58,225 pa

Hybrid Permanent

Senior Silicon Validation Engineer

This role involves leading the validation and characterisation of analogue and mixed-signal ASICs for trapped-ion quantum processors. Responsibilities include test planning, platform development, first-silicon bring-up, and system integration, with a focus on cryogenic testing and reusable automation.

IonQ Oxford

Senior Mixed Signal IC Design Enigneer

Design GaN power ICs and Si gate drivers using EDA tools, covering schematic capture, RTL, analog/digital and mixed-signal simulation, synthesis, STA, PNR and AMS verification. Also develops test solutions, analyses wafer-level and packaged device data, documents designs, debugs ICs and generates IP for patent applications within a growing R&D engineering team.

Cambridge GaN Devices Cambridge

On-site Permanent

Director of Packaging

Senior leadership role owning the packaging function for GaN power semiconductors, combining people leadership with hands-on design of wirebond, flip chip and embedded packages. Involves multiphysics simulation, supplier development, qualification testing and roadmap input, working with internal teams and overseas partners from the Cambridge office.

Cambridge GaN Devices Cambridge

On-site Permanent

Senior QPU Design Engineer

Integrate all features needed to operate quantum computers into complex multi-layer ion-trapping chips, guiding designs from requirements through layout and tape-out. Work closely with scientists and fabrication engineers on metal-track routing and photonics/CMOS interfaces, using GDSFactory in Python and Cadence. Hybrid role, three days per week in the Oxford office.

IonQ Oxford

Hybrid Clearance Required

Senior FPGA Engineer

Owns the full FPGA development lifecycle on a defence and aerospace programme, from requirements capture and architecture through VHDL implementation, verification and integration onto target hardware. Also leads and mentors other engineers, manages work packages to cost and quality targets, and reports progress to engineering leadership. Based fully on-site in Newport under SC clearance.

Belcan Newport £85 ph

On-site Contract Clearance Required

Engineer, Software and Electronics

Projects range from defence and security to robotics and consumer productsCambridge (fully onsite); to c£65,000 + Top BenefitsAre you interested in variety and keen to work on products that could be applied for industrial systems, UK military, or consumer products...

ECM Selection Cambridge £45,000 – £65,000 pa

Research Fellow in Advanced Semiconductor Device Modelling

Develops and validates predictive models of source-gated and multimodal transistors on an EPSRC project, using TCAD, compact modelling, surrogate modelling or physics-informed machine learning. Works closely with experimental researchers to fit models against measured data and inform device and circuit design, producing publications and reusable simulation frameworks.

University of Surrey Guildford £38,448 – £46,970 pa

Contract

Senior FPGA Engineer

Design, develop and verify FPGA solutions in VHDL across the full development lifecycle, from requirements capture and architecture definition to simulation, validation and hardware integration. You'll provide technical leadership within a multidisciplinary team on a Defence & Aerospace programme, using Xilinx, Altera or Microsemi devices with Vivado, Quartus II, ModelSim or Libero tooling.

Belcan Newport £85 ph

On-site Contract Clearance Required

PhD Engineer (summer 2027 start)

Join a multidisciplinary team building integrated software-hardware systems for defence and security, spanning low-power embedded devices to high-throughput server applications. You'll apply C/C++, FPGA, and electronics skills to complex projects combining custom hardware with innovative software, with labs and prototyping facilities on site.

ECM Selection Guildford £40,000 – £46,000 pa

On-site Clearance Required

Senior Staff CAD Engineer

Provides technical leadership for a global EDA/CAD compute and engineering infrastructure, spanning Linux environments, LSF batch compute, EDA license servers, Perforce and project/workspace provisioning. Combines hands-on Python and shell automation with architecture, monitoring and capacity planning, working across engineering, CAD and IT/IS teams to keep semiconductor development environments consistent and reliable worldwide.

Renesas Electronics Swindon

Hybrid Permanent

Senior Staff CAD Engineer

Provides technical leadership for a global EDA/CAD compute and engineering infrastructure, spanning Linux environments, LSF batch compute, EDA license servers, Perforce and project/workspace provisioning. Combines hands-on engineering with architecture and operational ownership, building Python and shell automation, monitoring dashboards and capacity planning. Works across engineering, CAD and IT/IS teams to keep environments scalable and globally consistent for semiconductor development.

Renesas Electronics Edinburgh

Hybrid Permanent

Senior HW Engineer – PCB Layout

Owns dense, high-layer-count PCB layout from schematic handoff to fabrication release, covering stackups, HDI structures, controlled-impedance routing, differential pairs and BGA breakout for large FPGAs and custom ASICs. Acts as the main technical contact with fabricators and assembly houses, and sets the footprint libraries, design rules and CAD standards the wider team works to.

Lumai Oxford

Hybrid Permanent

Senior HW Engineer – Signal and Power Integrity

Owns signal and power integrity across high-speed boards and packages, running pre-layout channel studies, post-layout SI analysis with IBIS-AMI models, and PDN impedance and DC drop work for high-current ASIC and FPGA rails. Channels span chip, package, interposer, board and optical engine, with heavy bench correlation using VNAs, TDRs and oscilloscopes to feed design rules.

Lumai Oxford

Hybrid Permanent

Senior Systems Engineer

Supports the development of advanced semiconductor manufacturing equipment across the full product lifecycle, translating product concepts into system requirements and architectures. Leads Integration, Verification & Validation activities and develops Functional, Logical and Behavioural models using MBSE approaches. Works under the Systems Engineering Manager within a multidisciplinary product development team.

Empresaria Group plc Bristol £70,000 – £85,000 pa