Senior Semiconductor Reliability Engineer – Advanced Silicon & Packaging

Graphcore
Bristol, United Kingdom
3 weeks ago
Job Type
Permanent
Work Pattern
Full-time
Work Location
On-site
Seniority
Senior
Education
Masters
Posted
6 May 2026 (3 weeks ago)

Benefits

Flexible working Generous annual leave

About Graphcore

At Graphcore, we’re building the future of AI compute. We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale. As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world. We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.

Job Summary

We are seeking a Senior Semiconductor Reliability Engineer to lead reliability strategy and execution across advanced silicon nodes and advanced packaging technologies, spanning both pre-silicon and post-silicon phases. This role is responsible for ensuring robust product reliability from technology selection and design enablement through silicon bring-up, qualification, and high-volume manufacturing.

The successful candidate will work at the intersection of device physics, circuit design, packaging, and manufacturing, providing technical leadership on reliability risk assessment, modeling, qualification, and failure analysis for complex, high-performance devices.

The Role

As a Senior Reliability Engineer, you will lead reliability strategy and qualification activities for advanced AI silicon and package technologies. You’ll work across pre-silicon analysis, post-silicon qualification, and failure analysis, partnering closely with silicon, packaging, manufacturing, and quality teams.

This role combines deep technical expertise with cross-functional leadership and offers the opportunity to influence reliability methodology for cutting-edge AI hardware platforms.


Responsibilities and Duties

  • Define reliability requirements for advanced silicon nodes and package platforms
  • Perform pre-silicon reliability risk assessments across silicon, interconnect, and package technologies
  • Evaluate reliability mechanisms including EM, TDDB, BTI, HCI, BEOL, and silicon-package interaction
  • Support design reviews, guard-banding, and reliability sign-off activities
  • Develop and execute qualification plans aligned with JEDEC and customer requirements
  • Lead HTOL, thermal cycling, thermal shock, and reflow qualification testing
  • Drive correlation between pre-silicon modelling and post-silicon qualification results
  • Lead root-cause analysis of silicon and package-related failures
  • Utilize X-ray and CSAM analysis to diagnose package defects including delamination, voiding, and cracking
  • Work with foundries, OSATs, and reliability labs to resolve reliability and manufacturing issues
  • Author qualification reports, risk assessments, and reliability documentation
  • Mentor engineers and contribute to reliability best practices and methodologies

Candidate Profile

Essential

  • Bachelor’s or Master’s degree in Electrical Engineering, Materials Science, Physics, Mechanical Engineering, or related field
  • 8+ years of semiconductor reliability engineering experience
  • Strong understanding of silicon reliability mechanisms including EM, TDDB, BTI, and HCI
  • Experience with BEOL, interconnect, and advanced package reliability
  • Hands-on experience with HTOL, thermal cycling, thermal shock, and reflow testing
  • Experience using X-ray and CSAM for package failure analysis
  • Familiarity with JEDEC reliability standards
  • Strong analytical, communication, and cross-functional collaboration skills

Desirable

  • Experience with leading-edge nodes, AI accelerators, or high-performance SoCs
  • Knowledge of HBM, chiplets, TSVs, micro-bumps, and 2.5D/3D integration
  • Experience with wafer-level reliability or system-level stress testing
  • Experience working with foundries and OSAT partners
  • Technical leadership or mentoring experience

Benefits

In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.

Applicants for this position must hold the right to work in the UK. Unfortunately at this time, we are unable to provide visa sponsorship or support for visa applications

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