Senior Design Verification Engineer

MicroTech Consulting
Cambridge, United Kingdom
3 days ago
Seniority
Senior
Education
Degree
Posted
2 Jun 2026 (3 days ago)

Benefits

25 days annual leave + 8 bank holidays Employer pension contribution Private medical insurance Income protection Critical illness and life cover Opportunities to attend industry conferences and training

An exciting opportunity has just opened for a Senior / Lead Verification Engineer to join a cutting-edge team in Cambridge, UK, driving innovation in next-gen semiconductor projects

Our client is expanding their DV team at a key growth stage, offering a rare opportunity tojoin early and genuinely shape verification methodology, standards, and technical direction as the team scales.

Position Overview
The work is focused onproduction-grade open-source silicon, including theIbex RISC-V CPU and OpenTitan security platform, developed in collaboration with world-leading partners such as Google. This is real silicon used as a foundation for secure and scalable compute systems.

Key Responsibilities

  • Design, implement, and debug block/system-level tests and testbenches using SystemVerilog and UVM
  • Develop test and coverage plans for new and updated designs
  • Triage and debug nightly regressions
  • Review contributions to open-source projects
  • Enhance test and CI infrastructure
  • Collaborate on academic/industry publications
  • Stay current with verification best practices and introduce improvements

Candidate Requirements

Essential:

  • 5+ years industry experience in design verification
  • StrongSystemVerilog and UVM expertise
  • Experience across the full verification cycle (planning to tape-out)
  • Able to provide estimates and coordinate with project managers
  • Comfortable in multidisciplinary, multi-organisation teams
  • Familiar with Git and code review tools (GitHub, GitLab, Gerrit)
  • Programming in C and/or Python for tests and automation
  • Undergraduate degree in a technical discipline or equivalent

Desirable:

  • Experience with multiple hardware block types
  • Knowledge of security countermeasures (fault injection, side-channel attacks)
  • Experience withRISC-V ISA or other instruction sets
  • Familiarity with formal verification tools (e.g., JasperGold)

Benefits

  • 25 days annual leave + 8 bank holidays
  • Employer pension contribution
  • Private medical insurance, income protection, critical illness and life cover
  • Opportunities to attend industry conferences and training

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