Physical Design Engineer Jobs UK 2026: ASIC Backend, STA and Place-and-Route Pay

The Short Answer

Physical Design (PD), sometimes called ASIC backend, is the discipline that turns a synthesised RTL netlist into a manufacturable GDSII layout. In the UK in 2026, it is one of the scarcer and better-paid corners of the chip industry, and demand has tightened as more domestic teams tape out at advanced nodes.

PD covers a chain of overlapping crafts — synthesis hand-off, floorplanning, placement, clock tree synthesis (CTS), routing, static timing analysis (STA), power and IR-drop, and physical signoff (DRC/LVS) — and most UK employers hire specialists rather than generalists. Pay bands in 2026 typically run from around £55,000 for a first PD role through £90,000–£130,000 for senior individual contributors, and up to roughly £160,000–£180,000 for staff and principal engineers at the largest design houses. Contract day rates during tape-out cycles regularly clear £700–£900, and we have seen the very top end of those rates indicated in public Indeed listings.

Top UK employers actively hiring in PD include Arm in Cambridge, Apple UK, Nvidia's Cambridge office, AMD UK, Qualcomm Cambridge, Intel UK, MediaTek UK, Samsung Cambridge, Imagination Technologies at Kings Langley, Pragmatic Semiconductor in Durham and Cambridge, Sondrel in Reading, Cirrus Logic in Edinburgh, Renesas in Edinburgh and Picocom in Bristol. The Department for Science, Innovation and Technology (DSIT) and its National Semiconductor Strategy continue to underpin the policy backdrop, and that has helped sustain hiring even when other engineering disciplines have softened.

This guide is a practical UK-focused walk through what PD actually involves in 2026, the sub-roles employers post, the pay bands we are seeing, the EDA tools that show up in job adverts, and how engineers from RTL, DFT or library teams can move across.

What Physical Design Actually Covers in 2026

PD is best understood as a pipeline rather than a single job. The flow usually looks like this:

• Synthesis hand-off. The PD team receives a gate-level netlist from front-end design, along with constraints (SDC), libraries and a target technology. Increasingly in 2026, that hand-off is iterative — synthesis is re-run as physical feedback comes back.

• Floorplanning. Macros, memories and IP blocks are placed; power grids are stitched; pin assignments are agreed with neighbouring blocks. At 5nm and below, floorplanning is where most timing and congestion problems are either prevented or baked in.

• Placement. Standard cells are placed with timing, congestion and power as the optimisation targets. Most UK teams use Synopsys IC Compiler II or Cadence Innovus, sometimes both for comparison.

• Clock tree synthesis (CTS). Clock skew, latency and on-chip variation are managed. CTS engineers are increasingly specialised because skew budgets at N5/N4P/N3 are punishing and multi-domain clocking is normal.

• Routing. Detailed routing in advanced nodes means dealing with multi-patterning rules, EUV constraints and extreme density. Hold fixing and signal integrity are typically interleaved.

• Static timing analysis (STA). Closure across hundreds or thousands of modes/corners is now standard, often using Synopsys PrimeTime or Cadence Tempus, with ECO loops feeding back into placement and routing.

• Power and IR-drop / EM analysis. Dynamic and static IR analysis tends to live with a power integrity specialist, particularly for AI accelerators and mobile SoCs.

• Physical signoff: DRC and LVS. Calibre nmDRC and nmLVS remain the dominant tools in UK signoff flows, with foundry decks for TSMC, Samsung and increasingly Intel Foundry.

The headline change in 2026 is that more UK teams are routinely working on N5, N4P and N3 designs, where double-patterning rules, EUV-aware routing and electromigration limits all interact. That has driven demand for engineers who have actually shipped at advanced nodes, not just simulated them.

Which PD Roles Are in Demand?

UK employers tend to post against fairly specific sub-roles rather than a generic "physical design engineer". The most common in 2026 are:

• Physical Design Engineer. The generalist title, usually expected to take a block from floorplan to signoff and own at least one of placement, CTS or routing.

• ASIC Backend Engineer. Often interchangeable with PD Engineer, particularly at consultancies and service houses. The "backend" framing tends to crop up at Sondrel, Pragmatic and at smaller design services firms.

• STA Engineer. Focuses on timing closure across PVT corners and modes. Strong demand at Arm, Apple and Nvidia in Cambridge, where multi-mode multi-corner (MMMC) flows are standard.

• CTS Engineer. Increasingly a discrete specialism; useful at large SoCs with multiple clock domains and aggressive skew targets.

• Power / IR Engineer. Owns dynamic and static IR drop, EM checks and power grid integrity. Common at AI silicon teams and at Imagination Technologies.

• Floorplanning Architect. A senior role typically held by engineers with 10+ years of experience; sets the partitioning, hierarchy and budgeting that the rest of PD relies on.

• DFT Engineer. Sits at the boundary of front-end and backend; scan, MBIST, JTAG and boundary scan insertion. We treat DFT as an adjacent specialism rather than core PD, but it is a common move into PD for engineers from the verification side.

What Do PD Roles Pay in the UK?

PD typically commands a premium over comparable RTL design roles because the supply of engineers with hands-on advanced-node tape-out experience is thinner. The numbers below are indicative ranges for 2026 — actual offers will vary by node, employer and London or Cambridge weighting.

• Junior / Graduate PD Engineer (0–2 years). Around £40,000–£55,000. MSc routes from Edinburgh, Imperial, Southampton, Manchester and UCL are the typical entry points.

• PD Engineer (2–5 years). Roughly £60,000–£85,000. Engineers who have shipped at least one tape-out at 7nm or smaller tend to sit in the upper part of that band.

• Senior PD / STA Engineer (5–10 years). Around £90,000–£130,000. This is where the supply gap is most obvious; counter-offers are common.

• Staff / Principal PD Engineer (10+ years). £140,000–£180,000 is plausible at Arm, Apple, Nvidia and Qualcomm in Cambridge, with equity or RSUs on top in several cases.

• Contract day rates. £600–£900 per day is typical for senior PD and STA contractors, with the higher end of that range generally indicated for tape-out crunch periods. Indeed UK listings for ASIC Physical Design contract work have shown rates in that bracket.

These are hedged figures rather than guarantees — the PD job market is small enough that a single competitive offer can move a band by 10–15% in either direction. We would treat PayScale's reported UK average for Physical Design Engineer (around £50,000) as skewed by job titles rather than reflective of senior specialists in the Cambridge cluster.

Top UK Employers Hiring

The UK PD employer base in 2026 is concentrated around Cambridge, with secondary clusters in Edinburgh, Bristol, Reading, Kings Langley and Durham. The names worth tracking include:

• Arm, Cambridge. Probably the single largest PD employer in the UK; consistent hiring across PD, STA, CTS and DFT.

• Apple UK. Cambridge and London silicon teams; hires senior PD and STA engineers for custom SoC work.

• Nvidia UK, Cambridge. Expanded networking and AI silicon teams; PD hiring across multiple seniority bands.

• AMD UK. Hiring into Cambridge and other UK sites for both CPU and GPU PD work.

• Qualcomm, Cambridge. Long-standing modem and connectivity PD team.

• Intel UK. PD and signoff roles tied to client and foundry programmes.

• MediaTek UK. Growing UK PD presence supporting connectivity and SoC work.

• Samsung, Cambridge. AI and SoC PD roles based out of the Cambridge research site.

• Imagination Technologies, Kings Langley. GPU and AI accelerator PD, including power and IR specialists.

• Pragmatic Semiconductor, Durham and Cambridge. Flexible-integrated-circuit work; useful for engineers who want exposure to a non-traditional process.

• Sondrel, Reading. ASIC design services house; broad PD exposure across customer projects.

• Cirrus Logic, Edinburgh. Mixed-signal SoCs with PD roles tied to audio silicon.

• Renesas, Edinburgh. Following its Dialog acquisition, continues to hire PD and STA engineers in Scotland.

• Picocom, Bristol. Open RAN small-cell silicon; smaller PD team but active hiring.

Several of these employers — particularly Arm, Imagination, Pragmatic and Sondrel — explicitly reference the UK's industrial base when justifying hiring plans, which lines up with the DSIT National Semiconductor Strategy's emphasis on design and IP as UK strengths.

Tools UK Employers Are Asking For

Job adverts in 2026 are reasonably consistent on the tooling expected. The recurring stack is:

• Place and route. Synopsys IC Compiler II and Cadence Innovus. Most senior PD job adverts ask for one and prefer both.

• Static timing analysis. Synopsys PrimeTime is the dominant STA tool in UK adverts, with Cadence Tempus appearing more often at Cadence-aligned shops.

• Physical signoff. Calibre nmDRC and Calibre nmLVS from Siemens EDA remain the de facto standard for UK PD signoff.

• Power and IR. Ansys RedHawk-SC and Synopsys PrimePower / PrimeRail show up in advanced-node adverts.

• Parasitic extraction. Synopsys StarRC and Cadence Quantus.

• Languages and scripting. Tcl is non-negotiable, Python is increasingly assumed, and Perl still lingers in legacy flows.

• Process nodes. Job adverts frequently call out N5, N4P and N3 experience, and occasionally 16nm/12nm for IoT and edge silicon. Engineers with shipped tape-out experience at 5nm or below are clearly the most sought-after group.

Engineers without exposure to the latest nodes can still compete on STA, CTS and signoff roles, where flow expertise often matters more than node bleeding-edge experience.

How to Break In From Adjacent Specialisms

PD is not a discipline most engineers walk into directly from university, though a handful of MSc routes (notably from Edinburgh, Southampton, Imperial and UCL) feed straight into graduate PD programmes at Arm, Imagination and Sondrel. More commonly, engineers move sideways from:

• RTL / Front-end Design. The most natural transition. Engineers who already understand timing constraints, clock domain crossing and synthesis usually convert quickly into STA or PD generalist roles. Highlight any synthesis, SDC and gate-level work in the CV.

• DFT Engineering. DFT sits at the boundary, and engineers who have done scan insertion and ATPG tend to have credible PD-adjacent experience. STA and signoff roles are the easiest first move.

• Library / IP Characterisation. Engineers from standard-cell or memory IP teams already understand library views, PVT corners and characterisation flows; many move into STA, signoff or power integrity.

• Verification. A longer route, but UVM-trained engineers with gate-level simulation experience can move into STA, then PD.

• Fresh-grad MSc routes. Look for MSc dissertations or projects that involve hands-on use of an EDA tool — even an open-source flow like OpenROAD — as that materially de-risks the hire for employers.

For most engineers contemplating the move in 2026, the practical advice is to target STA or CTS as a first PD role, rather than trying to land a full-flow PD Engineer post in one step. STA is closer to the front-end mental model and translates well from RTL work, while CTS demand is unusually high relative to supply.

Frequently Asked Questions: PD Jobs UK

Is physical design a good career in the UK in 2026?

It is one of the more defensible specialisms in the UK chip industry. Demand is concentrated but persistent, the supply of senior engineers is thin, and pay sits comfortably above comparable RTL roles. The DSIT National Semiconductor Strategy continues to single out design and IP as UK strengths, which we read as supportive of medium-term PD hiring.

Do I need a PhD to work in physical design?

No. The majority of UK PD adverts ask for a BEng or MSc in electronic engineering or a related discipline. A PhD is helpful for research-oriented roles at Arm Research or Imagination but is not required for mainstream PD, STA or CTS positions.

Where are the UK PD jobs concentrated?

Cambridge is the clear centre of gravity, followed by Edinburgh (Cirrus Logic, Renesas), Bristol (Picocom and adjacent design services), Reading (Sondrel) and Kings Langley (Imagination). Smaller pockets exist in London, Manchester, Belfast and Sheffield.

Can I work remotely as a UK PD engineer?

Partially. Most UK employers have moved to hybrid arrangements — typically two or three days on site — and tape-out periods often require closer in-person collaboration. Fully remote PD roles do exist, particularly for senior STA and signoff engineers, but they remain the exception.

How long does it take to become a senior PD engineer?

In practice, five to eight years from a first PD role is a realistic timeline to a senior individual contributor position at a UK design house, assuming exposure to at least two full-flow tape-outs. Staff and principal grades typically require ten or more years and demonstrable ownership of large blocks or full chips.

Are contract PD roles still common in the UK?

Yes. Day rates of £600–£900 are typical for senior PD and STA contractors in 2026, with the higher end seen during tape-out crunch and at advanced nodes. Inside-IR35 determinations are now the norm at large employers, which has compressed take-home pay but not eliminated demand.

Summary

Physical design remains one of the better paid and more defensible specialisms in the UK chip industry in 2026. Pay bands run from roughly £55,000 at entry to £180,000 at staff and principal level, with contract rates of £600–£900 per day for senior PD and STA work. The employer base is concentrated in Cambridge but extends to Edinburgh, Bristol, Reading, Kings Langley and Durham, and the policy backdrop — anchored by DSIT and the National Semiconductor Strategy — continues to support hiring. Engineers from RTL, DFT and library backgrounds have plausible paths in, particularly via STA or CTS. The tooling expectation is reasonably stable around IC Compiler II, Innovus, PrimeTime, Tempus and Calibre, with advanced-node experience at N5, N4P and N3 the clearest differentiator.

Browse current UK physical design, ASIC backend, STA and place-and-route vacancies at semiconductorjobs.co.uk — the UK's specialist semiconductor job board.