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£46,049 – £58,225 pa Hybrid Permanent

Senior Analog / Mixed-Signal Design Engineer

This role involves designing and integrating analog/mixed-signal circuits for advanced semiconductor packaging and heterogeneous integration. Responsibilities include PHY-level interfaces, custom pad circuits, and working with industry partners to develop and commercialize innovative solutions.

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University of Southampton

Southampton

Clearance Required

Semiconductor Test Engineering Team Leader

Lead manufacturing test strategy and silicon production readiness for next-generation AI accelerator chips, covering DFT, ATE bring-up, characterisation, yield optimisation and advanced packaging test. Manages an internal team of test engineers plus external OSAT and ATE partners, working closely with design, DFT, packaging and validation groups.

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Fractile

Bristol

Clearance Required

Processor Architect

Define and own the architecture of core compute engines, from ISA and programming models to memory hierarchies and on-chip interconnects. Work hands-on in performance modelling, specification writing, bottleneck analysis and pre/post-silicon validation alongside logical design, physical design and verification teams. Acts as a technical mentor and represents compute engine architecture in reviews and customer engagements.

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Fractile

London

Senior Silicon Validation Engineer

This role involves leading the validation and characterisation of analogue and mixed-signal ASICs for trapped-ion quantum processors. Responsibilities include test planning, platform development, first-silicon bring-up, and system integration, with a focus on cryogenic testing and reusable automation.

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IonQ

Oxford

On-site Permanent

Senior Mixed Signal IC Design Enigneer

Design GaN power ICs and Si gate drivers using EDA tools, covering schematic capture, RTL, analog/digital and mixed-signal simulation, synthesis, STA, PNR and AMS verification. Also develops test solutions, analyses wafer-level and packaged device data, documents designs, debugs ICs and generates IP for patent applications within a growing R&D engineering team.

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Cambridge GaN Devices

Cambridge

£85 ph On-site Contract Clearance Required

Senior FPGA Engineer

Owns the full FPGA development lifecycle on a defence and aerospace programme, from requirements capture and architecture through VHDL implementation, verification and integration onto target hardware. Also leads and mentors other engineers, manages work packages to cost and quality targets, and reports progress to engineering leadership. Based fully on-site in Newport under SC clearance.

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Belcan

Newport

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