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Physical Design Engineer Jobs

Engineers who optimise the layout and performance of semiconductor chips. A critical role in the semiconductor design flow, ensuring that circuits meet performance and manufacturability requirements.

Open roles
6
Hiring companies
1
View 6 live roles → Get an alert

Physical Design Engineers (PD Engineers) play a pivotal role in the semiconductor industry, focusing on the layout and optimisation of integrated circuits (ICs). They work closely with design teams to ensure that the physical layout of the chip meets performance, power, and area constraints. PD Engineers are essential in the design flow, from initial floorplanning to final verification, ensuring that the chip is both functional and manufacturable. This role is highly technical and requires a deep understanding of both digital and analog design principles, as well as advanced CAD tools.

What the role does

Inside the role of a Physical Design Engineer

A typical week for a PD Engineer is a mix of design, simulation, and collaboration with other teams. They spend a significant amount of time using CAD tools to create and optimise chip layouts.

  1. 01
    Analyse design requirements and constraints.
  2. 02
    Create and optimise chip layouts using CAD tools.
  3. 03
    Run simulations to verify performance and manufacturability.
  4. 04
    Collaborate with design and verification teams.
  5. 05
    Document design decisions and changes.
  6. 06
    Attend project meetings and provide updates.
Skills & tools

What hiring managers ask for

% of 6 listings posted in the last 12 months that mention each skill, extracted from job descriptions.

Cadence Innovus
100%
Mentor Graphics Calibre
100%
TCL
100%
Perl
100%
Python
100%
Power Planning
83%
AI Accelerators
83%
Networking Chips
83%
Floorplanning
67%
Clock Tree Synthesis (CTS)
67%
Routing
67%
Synthesis
67%
Career ladder

From Junior to Principal

A typical UK progression for physical design engineers. Years are guidance — strong people move faster, and many senior folks sidestep into research, product or management.

  1. Level 1

    Junior Physical Design Engineer

    0–2 yrs

    Assists in the creation and optimisation of chip layouts under supervision. Focuses on learning the design flow and CAD tools.

  2. Level 2

    Physical Design Engineer

    2–5 yrs

    Takes ownership of specific blocks or modules in the design. Responsible for meeting performance and manufacturability targets.

  3. Level 3

    Senior Physical Design Engineer

    5–10 yrs

    Leads the physical design of complex chips. Mentors junior engineers and collaborates with cross-functional teams.

  4. Level 4

    Principal Physical Design Engineer

    10+ yrs

    Oversees the physical design of entire chip projects. Provides strategic direction and drives innovation in design methodologies.

Pathway

How to become a Physical Design Engineer

There's no single route, but most people follow some version of these steps.

  1. 1

    Learn the Basics

    Gain foundational knowledge in semiconductor design and CAD tools. Understand the design flow and basic layout principles.

  2. 2

    Specialise in Physical Design

    Focus on physical design techniques and tools. Develop expertise in layout optimisation and verification.

  3. 3

    Gain Practical Experience

    Work on real projects, taking ownership of specific blocks or modules. Collaborate with design and verification teams.

  4. 4

    Lead Complex Designs

    Take on leadership roles in physical design. Lead the design of complex chips and mentor junior engineers.

  5. 5

    Strategic Direction

    Provide strategic direction for physical design projects. Drive innovation in design methodologies and tools.

Live jobs

6 live roles

Fractile logo

Physical Design Engineer

This role involves the physical implementation of advanced ASIC/SoC designs, covering floor planning, placement, clock tree synthesis, routing, and sign-off. The engineer will optimise for performance, power, and area using EDA tools and collaborate with RTL, verification, and process teams. A key focus is integrating physical design with AI-enhanced workflows and ensuring manufacturability through DRC, LVS, and DFT compliance.

Fractile London, United Kingdom
On-site Permanent
Fractile logo

Physical Design Engineer

This role involves implementing physical designs for advanced AI chips, covering floor planning, placement, clock tree synthesis, routing, and sign-off. The engineer will optimise for performance, power, and area using EDA tools and collaborate with design, verification, and process teams. The position integrates AI tools into the design flow and supports physical-aware RTL development.

Fractile Bristol, United Kingdom
On-site Permanent
Fractile logo

Lead Physical Design Engineer

This role involves leading the end-to-end physical implementation of advanced AI accelerator chips, from synthesis and floorplanning to sign-off, with full responsibility for PPA optimisation, power integrity, and physical verification. The engineer will lead teams, mentor junior staff, and develop EDA flows using tools like Innovus and Fusion Compiler, while collaborating closely with RTL, architecture, and DFT teams. A key focus is leveraging AI-driven methodologies to enhance design quality and productivity in a tightly integrated full-stack environment.

Fractile Bristol, United Kingdom
On-site Permanent
Fractile logo

Lead Physical Design Engineer

This role involves leading the end-to-end physical implementation of advanced ASIC/SoC chips, from synthesis and floorplanning to sign-off, with a focus on optimising performance, power, and area. The engineer will work closely with RTL, DFT, and process teams, using EDA tools and advanced AI techniques to enhance design quality and productivity. Full-chip ownership and collaboration across disciplines are key aspects of the position.

Fractile London, United Kingdom
On-site Permanent
Fractile logo

Senior/Principal Physical Design Engineer

This role involves end-to-end physical implementation of advanced ASIC/SoC designs for AI accelerators, including floorplanning, placement, clock tree synthesis, routing, and sign-off. The engineer will optimise for performance, power, and area (PPA) using industry-standard EDA tools and collaborate closely with RTL, architecture, and process technology teams. Focus areas include timing closure, low-power design, and manufacturability for cutting-edge nodes like 7nm and below.

Fractile London, United Kingdom
On-site Permanent
Fractile logo

Senior/Principal Physical Design Engineer

This role involves leading the physical implementation of advanced ASIC/SoC designs for AI accelerators, from synthesis through to sign-off. The engineer will focus on optimizing performance, power, and area using state-of-the-art EDA tools and deep expertise in low-power design and timing closure. Collaboration with RTL, DFT, and process teams is key to ensuring design integrity and manufacturability at advanced nodes.

Fractile Bristol, United Kingdom
On-site Permanent
Hiring locations

Where this role is hiring

The locations with the most live listings for this role today.

London

Location
3 open

Bristol

Location
3 open
FAQs

Common questions

  • Essential skills include a strong understanding of semiconductor design principles, proficiency in CAD tools, and the ability to collaborate effectively with cross-functional teams.

  • Career progression typically starts with a junior role, advancing to a senior position, and eventually leading to a principal or lead role, where you oversee entire chip projects and drive innovation.

  • Key challenges include meeting performance and manufacturability constraints, managing design complexity, and staying current with rapidly evolving technology and tools.

  • Stay updated by attending industry conferences, participating in professional development courses, and engaging with online communities and forums focused on semiconductor design.

  • Salary ranges can vary based on experience, location, and company size. For specific salary information, please refer to the salary section on this page.

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