Hexwired Recruitment Limited
FPGA Engineer
- Bristol
- £65,000 – £75,000 pa
- Senior
Designs RTL for next-generation communication systems, working on both FPGA and ASIC platforms using Verilog or SystemVerilog. The role sits within an expanding electronics manufacturer and calls for signal processing or digital communications knowledge plus scripting, typically in Python.
Verilog · SystemVerilog · Python