Design verification Engineer

We are looking for experienced SoC Design Verification (DV) Engineers to work on the verification of a next-generation, multi-die System-on-Chip (SoC) design.

Engineers will be responsible for subsystem-level and SoC-level functional verification using System Verilog/UVM methodology, as well as processor-driven verification using C-based test programs executing on embedded processor cores.

The role requires strong debugging and analytical skills, an understanding of ARM processor based SoC architecture, and the ability to efficiently adapt existing verification environments to evolving design requirements.

Key Responsibilities-

Required Technical Skills

Essential Skills

* Strong hands-on experience in digital design verification using System Verilog and UVM.

* Experience working with existing UVM testbenches, including modifying, extending, and debugging reusable verification components.

* Good understanding of constrained-random verification, functional coverage, assertions, scoreboards, and checkers.

* Experience in subsystem-level or SoC-level functional verification.

* Strong understanding of SoC architectures, bus protocols, register interfaces, and processor-controlled peripherals.

* Experience developing, executing, or debugging embedded C tests for processor-based SoC verification.

* Ability to debug complex RTL simulation failures using industry-standard simulators and waveform debugging tools.

* Experience executing regressions, analyzing failures, and driving functional coverage closure.

* Working knowledge of scripting languages such as Python, Perl, or shell scripting.

* Familiarity with version control systems and verification development workflows