Step 1: Define Role Clusters & Your Keyword Map

Titles vary wildly. Build clusters so your searches catch synonyms and adjacent roles.

Front-End Process Engineering (FEOL/BEOL)

• Areas: photolithography, etch (RIE/ICP), deposition (PVD/CVD/ALD/PECVD/MOCVD), diffusion/implant, wet cleans, CMP.

• Tools: ASML, TEL, Lam Research, Applied Materials, KLA/Hitachi CD-SEM, Nova/OCD, Rudolph/ellipsometry, Edwards vacuum.

• Methods: SPC/DOE/JMP, run-to-run control, APC/FDC, excursion management, contamination control (ISO 14644).

Equipment Engineering & Maintenance

• Topics: preventive/corrective maintenance, vacuum systems (HV/UHV), RF generators & matching networks, plasma sources, wafer handling robots/EFEM, CMMS, OEE, MTBF/MTTR, spares.

• Interfaces: PLC/HMI, SECS/GEM, E84, SMIF/FOUP.

Lithography & Photo

• Keywords: resist/process windows, overlay, focus-exposure, CD control, pellicles, reticles, stepper/scanner optimisation, track systems (coater/developer), alignment/metrology.

Etch & Deposition

• Etch: endpoint detection, polymer control, selectivity, profile tuning.

• Deposition: ALD cycles, conformality, MOCVD for GaN/GaAs, stress/wafer bow, film characterisation (XRR, XRD, ellipsometry).

CMP & Metrology

• CMP: pad/slurry selection, dishing/erosion, topography, post-CMP cleans.

• Metrology: CD-SEM, AFM, scatterometry, overlay, thickness/uniformity mapping.

Yield, Defect Engineering, Reliability & Failure Analysis

• Yield/Defect: Pareto, inline/wafer sort correlation, KLA/optical inspections, particle sources, SPC.

• Reliability: HTOL, HAST, temp cycle, ESD/latch-up, NBTI/TDDB/EM; JEDEC & AEC-Q100/101.

• Failure Analysis: FIB cross-section, SEM/TEM/EDX, nanoprobing, OBIRCH/TIVA/PICA, EBIC, micro-Raman/FTIR, de-cap/CSAM.

Device/Technology Development

• Keywords: WAT/PCM, Id-Vg/Id-Vd, leakage, breakdown, Rds(on), threshold, mobility; TCAD (Synopsys Sentaurus, Silvaco Atlas), compact models (BSIM), split experiments, epi, SiC/GaN devices.

Test & Product Engineering (ATE)

• Platforms: Advantest V93000, Teradyne UltraFLEX/J750, NI STS; probers/handlers.

• Topics: test programme dev, characterisation, correlation, DFT/BIST/JTAG/scan, shmoo, binning/yield ramps, load-board design.

Packaging, Assembly & OSAT

• Processes: dicing/singulation, wire bond, flip-chip/FCBGA, WLCSP/FOWLP, underfill, lid attach, mould/encap, thermal/warpage.

• Standards: JEDEC J-STD-020/MSL, reliability (THB/TC/HTS), automotive qualifications.

EDA & IC Design (Digital/Analog/RF/Silicon Photonics)

• Digital: RTL (SystemVerilog/VHDL), UVM, Synthesis/STA (DC/PrimeTime), P&R (Innovus/ICC2), DFT (Tessent), sign-off (Calibre DRC/LVS, StarRC, Voltus/RedHawk).

• Analog/RF: Virtuoso, PCells/layout, Spectre/Eldo/HSPICE, noise/linearity, PLL/ADC/DAC/PA/LNA, EM/IR/PEX, matching.

• Photonics: Lumerical/INTERCONNECT, IPKISS, grating couplers, AWGs, modulators, fibre attach.

Photonics, MEMS & Sensors

• Photonics: lasers, modulators, coupling/alignment, low-loss waveguides.

• MEMS: DRIE, wafer bonding, hermetic packaging, inertial/pressure/micro-mirror devices.

Fab Software, Automation & Data

• MES (Camstar/Promis), dispatching, WIP/Cycle time; SECS/GEM, EDA/Interface A, E142; FDC/APC; Python/SQL dashboards; yield analytics.

Quality, Automotive & Supply Chain

• Standards: ISO 9001, IATF 16949, APQP/PPAP, control plans, PFMEA/DFMEA, 8D, supplier audits.

UK Locations & Modes

• Cambridge, Oxford, Bristol/Bath, Reading/Thames Valley, Newport (South Wales compound-semi cluster), Sheffield, Manchester, Durham/Newcastle, Edinburgh/Glasgow, Belfast.

• Modes: On-site (fab/FA), Hybrid (test/product/yield), Remote UK (EDA/design sometimes).

• Modifiers: “Security clearance/SC/DV”, “Visa sponsorship”, “Graduate”, “Internship”, “Permanent”.

Capture this keyword map—you’ll reuse it across alerts, feeds and prompts.

Step 2: Build Precise Boolean Searches (Copy & Paste)

Use these in Google & on job boards. Start broad, then refine with site: filters where signal lives.

General UK Semiconductor

(semiconductor OR "wafer fab" OR foundry OR "IC design" OR "device engineer")
(process OR equipment OR lithography OR etch OR deposition OR "CMP" OR metrology OR "yield" OR "ATE" OR packaging OR "EDA")
(UK OR "United Kingdom" OR Cambridge OR Bristol OR Oxford OR Newport OR Manchester OR Edinburgh OR Glasgow OR Sheffield OR Durham)
("Permanent" OR "Full-time") -site:indeed.co.uk -site:glassdoor.co.uk

Front-End Process

("Process Engineer" OR "Process Development") (lithography OR etch OR ALD OR CVD OR PVD OR CMP OR implant OR diffusion) (SPC OR DOE) (UK OR "Remote UK")

Lithography

(lithography OR photo OR "photoresist") (ASML OR "overlay" OR "focus exposure" OR "CD") (UK OR "Remote UK")

Etch & Deposition

(etch OR RIE OR ICP OR deposition OR ALD OR CVD OR PECVD OR MOCVD) (selectivity OR "endpoint" OR conformality) (UK OR "Remote UK")

CMP & Metrology

(CMP OR "chemical mechanical") (slurry OR dishing OR erosion) (metrology OR "CD-SEM" OR scatterometry OR ellipsometry) (UK OR "Remote UK")

Equipment Engineering

("Equipment Engineer" OR maintenance) (vacuum OR plasma OR "RF generator" OR "matching network" OR "EFEM" OR "robot") (SECS/GEM OR PLC) (UK OR "Remote UK")

Yield/Defect/Reliability

("Yield Engineer" OR "Defect Engineer" OR "Reliability Engineer")
(SPC OR Pareto OR HTOL OR HAST OR "latch-up" OR ESD OR "AEC-Q100")
(UK OR "Remote UK")

Failure Analysis

("Failure Analysis" OR "FA Engineer") (FIB OR SEM OR TEM OR OBIRCH OR TIVA OR nanoprobe OR CSAM) (UK OR "Remote UK")

Device/TCAD

("Device Engineer" OR "Technology Development") (TCAD OR Sentaurus OR Silvaco OR "compact model" OR "WAT" OR epi) (UK OR "Remote UK")

Test & Product (ATE)

("Test Engineer" OR "Product Engineer") (Advantest OR Teradyne OR "test program" OR "characterisation" OR DFT OR JTAG OR scan) (UK OR "Remote UK")

Packaging/Assembly

(packaging OR OSAT OR "flip-chip" OR "WLCSP" OR FOWLP OR "wire bond" OR underfill OR dicing) (JEDEC OR "J-STD-020" OR MSL) (UK OR "Remote UK")

EDA & IC Design

("Digital Design" OR "Physical Design" OR "STA" OR "Analog" OR RF OR "Verification")
(SystemVerilog OR UVM OR "PrimeTime" OR Innovus OR ICC2 OR Calibre OR Virtuoso OR Spectre OR HSPICE)
(UK OR "Remote UK")

Photonics & MEMS

("Silicon Photonics" OR photonics OR MEMS) (Lumerical OR IPKISS OR "DRIE" OR "wafer bonding" OR "grating coupler") (UK OR "Remote UK")

Fab Software & APC

("MES" OR "SECS/GEM" OR "Interface A" OR "FDC" OR "APC") (Promis OR Camstar OR E142 OR E84 OR "Python" OR SQL) (UK OR "Remote UK")

Graduate & Early Career

("Graduate" OR "Junior" OR "Internship") (semiconductor OR "IC design" OR lithography OR "test engineer" OR photonics OR MEMS) (UK OR "Remote UK")

ATS & Employer Career Sites (cuts aggregator noise)

(semiconductor OR "IC design" OR "wafer fab" OR photonics OR MEMS)
(site:boards.greenhouse.io OR site:lever.co OR site:workable.com OR site:ashbyhq.com OR site:smartrecruiters.com OR site:icims.com OR site:successfactors.com)
(UK OR "Remote UK")

Academic & Labs

("semiconductor" OR photonics OR MEMS) (postdoc OR "research engineer" OR "research fellow")
(site:jobs.ac.uk OR site:cam.ac.uk OR site:ox.ac.uk OR site:ed.ac.uk OR site:hw.ac.uk)
(UK)

Step 3: Turn Searches Into Google Alerts & RSS

Let roles come to you.

Setup (quick)

1. Open Google Alerts.

2. Paste a Boolean string.

3. Show options → pick At most once a day (or As-it-happens if you’re sprinting).

4. Deliver to: choose RSS feed (paste into Feedly/Inoreader) or email.

5. Create separate alerts per cluster: Process, Equipment, Litho, Etch/Dep, CMP/Metrology, Yield/FA/Rel, Device/TCAD, ATE Test/Product, Packaging/OSAT, EDA/Design, Photonics/MEMS, Fab Software, Graduate.

Good alert examples (copy-paste):

("Process Engineer") (lithography OR etch OR ALD OR CVD OR CMP) (SPC OR DOE) (UK OR "Remote UK")

("Equipment Engineer" OR maintenance) (vacuum OR plasma OR "RF generator" OR "EFEM") (SECS/GEM) (UK OR "Remote UK")

("Yield Engineer" OR "Failure Analysis") (HTOL OR HAST OR OBIRCH OR FIB OR "AEC-Q100") (UK OR "Remote UK")

("Test Engineer" OR "Product Engineer") (Advantest OR Teradyne OR DFT OR JTAG OR "test program") (UK OR "Remote UK")

("Digital Design" OR "Analog IC" OR "Physical Design") (UVM OR PrimeTime OR Innovus OR Virtuoso OR Calibre) (UK OR "Remote UK")

Pro tips

• One alert per intent = cleaner results.

• Pair locations sensibly: Cambridge/Oxford/Bristol + “Remote UK” catch many roles; add Newport (compound-semis), Edinburgh/Glasgow, Sheffield/Manchester.

• Mute noisy domains with -site: to keep feeds focused.

Prefer RSS? Tag/star items & export starred roles as CSV—perfect for a weekly planning pass with ChatGPT.

Step 4: Use ChatGPT as Your “Semiconductor Job Scout”

Alerts & RSS deliver raw listings. ChatGPT turns them into a ranked shortlist with actions so you apply faster & better.

Reusable system prompt (edit to your targets):

System role: You are my Semiconductor Job Scout for UK roles. Parse pasted job listings (title, company, location, link, snippet), remove duplicates by company+title+location, and produce a ranked shortlist that matches my criteria. Then provide tailored actions for each role.

My criteria:
• Target clusters: Process (FEOL/BEOL), Equipment, Litho, Etch/Dep, CMP/Metrology, Yield/Defect/Rel, Failure Analysis, Device/TCAD, Test/Product (ATE), Packaging/OSAT, EDA/IC Design, Photonics/MEMS, Fab SW/APC.
• Must-haves by cluster:
  - Process: SPC/DOE, excursion control, tool & recipe ownership, inline→WAT→sort correlation.
  - Equipment: HV/UHV, plasma/RF, robot/EFEM, SECS/GEM, MTBF/MTTR/OEE improvements.
  - Litho: overlay/CD control, resist/process windows, scanner/track optimisation.
  - Etch/Dep: selectivity/profile, endpoint, conformality/stress; ALD/MOCVD for GaN/SiC.
  - CMP/Metrology: pad/slurry tuning, dishing/erosion control, CD-SEM/OCD/AFM/overlay.
  - Yield/Rel: Pareto/SPC, HTOL/HAST/ESD, AEC-Q100/101/JEDEC quals.
  - FA: FIB/SEM/TEM, OBIRCH/TIVA/PICA, nanoprobing, de-cap/CSAM.
  - Device/TCAD: Sentaurus/Silvaco, WAT/PCM, compact models, epi/process splits.
  - Test/Product: Advantest/Teradyne, DFT/JTAG/scan, characterisation/correlation, load-boards.
  - Packaging/OSAT: flip-chip/WLCSP/FOWLP, underfill/warpage, JEDEC J-STD-020/MSL, reliability.
  - EDA/IC: UVM, Synthesis/STA, P&R, DRC/LVS/PEX, Virtuoso analog, sign-off.
  - Photonics/MEMS: Lumerical/IPKISS, DRIE/bonding, coupling/low-loss waveguides.
  - Fab SW: MES/SECS-GEM/Interface-A, FDC/APC, Python/SQL dashboards.
• Location: Remote UK or Cambridge/Oxford/Bristol/Newport/Manchester/Edinburgh/Glasgow hybrid.
• Exclude: pure sales, contract <3 months, agency spam.

Output:
1) Summary: counts & duplicates removed; scoring logic in 2 lines.
2) Ranked Shortlist (max 10): Title — Company — Location — Link — Score (0–100) — 1–2 line fit rationale.
3) Per-role actions:
   - 3 tailored CV bullets (impact-led, tools/process & outcomes).
   - 6–10 keywords to mirror (equipment, methods, standards, metrics).
   - A 3-sentence message to the hiring contact referencing one concrete requirement.
4) Today plan: order to apply with time estimates.

Daily run (paste your feed)

Here are today’s roles (Title — Company — Location — Link — Snippet):
1) ...
2) ...
Apply the Semiconductor Job Scout system prompt.

Deep-dive on a single role (for the perfect match)

Analyse this spec for must-haves, repeated terms & implied priorities. Then:
• Write 3 CV bullets that mirror the spec (cluster-appropriate), each ending with a measurable outcome.
• Draft a 120-word cover note referencing one tool/process/standard & a 30-day quick win.
• List 10 keywords/phrases to include naturally (equipment, methods, standards, metrics).
• Provide 6 likely interview questions with succinct model answers using my background.

Job spec: [paste]
My background: [4–8 bullets with tools/process/metrics & outcomes]

Fast CV tailoring prompts (cluster-specific)

Process (FEOL/BEOL)

Create 5 “Recent Impact” bullets showing recipe ownership (litho/etch/dep/CMP), SPC/DOE, excursion response & inline→WAT correlations—each with % yield or defect reduction. UK spelling.
Spec: [paste]

Equipment

Produce 5 bullets on HV/UHV & plasma/RF fault-finding, EFEM/robot maintenance, SECS/GEM integration & MTBF/MTTR/OEE improvements—each with quantified gains.
Spec: [paste]

Lithography

Write 5 bullets covering overlay/CD control, focus-exposure matrix, resist/process windows & scanner/track optimisation—each with CDU/overlay metrics.
Spec: [paste]

Etch/Dep

Draft 5 bullets on selectivity/profile/AR control, endpoint strategies, ALD/MOCVD conformality & film stress—each with uniformity or device param improvements.
Spec: [paste]

CMP/Metrology

Output 5 bullets on pad/slurry tuning, dishing/erosion minimisation, post-CMP cleans & CD-SEM/OCD/AFM correlations—each with topography/yield metrics.
Spec: [paste]

Yield/FA/Rel

Provide 5 bullets on Pareto/SPC, HTOL/HAST/ESD quals, OBIRCH/FIB/TEM root-cause & 8D closures—each with DPPM/FIT or cycle-time reductions.
Spec: [paste]

Device/TCAD

Create 5 bullets on Sentaurus/Silvaco process/device sims, WAT splits & compact modelling—each tied to Rds(on)/Vth/leakage/fidelity metrics.
Spec: [paste]

Test/Product (ATE)

Write 5 bullets on V93000/UltraFLEX test programme dev, DFT (scan/JTAG/BIST), board bring-up, char/correlation/guardbanding—each with yield/UPH/test-time metrics.
Spec: [paste]

Packaging/OSAT

Produce 5 bullets on flip-chip/WLCSP/FOWLP, underfill/warpage control, JEDEC J-STD-020/MSL & reliability quals—each with yield/return-rate improvements.
Spec: [paste]

EDA/IC Design

Draft 5 bullets on UVM verification, Synthesis/STA, P&R closure & sign-off (DRC/LVS/PEX/EMIR)—each with timing/area/power wins.
Spec: [paste]

Fab Software/APC

Write 5 bullets on MES/SECS-GEM/Interface-A integration, FDC/APC deployments & Python/SQL yield analytics—each with cycle-time or scrap reduction metrics.
Spec: [paste]

Step 5: Optional No-Code Automation (Email, Slack, Notion)

• Email filters: Route alert emails to a “Semi-Jobs” label. Each morning, paste the best items into ChatGPT and run your Job Scout prompt.

• RSS rules: Tag feeds by cluster (Process/Equipment/Litho/Etch/CMP/Yield/FA/Device/Test/Packaging/EDA/Photonics/Fab SW). Star the best and export weekly as CSV for a planning pass.

• Notion/Sheets: Keep one tracker; paste it into ChatGPT for daily prioritisation and follow-up drafting.

• Slack/Discord: Pipe starred roles via webhook into a private channel for quick triage.

Step 6: A Simple Pipeline Tracker That Wins Interviews

Suggested columns

• Date found

• Role

• Company

• Location

• Link

• Cluster (Process/Equipment/Litho/Etch/CMP/Yield/FA/Device/Test/Packaging/EDA/Photonics/Fab SW)

• Match score (0–100)

• Status (To apply / Applied / Interview / Offer / On hold / Rejected)

• Deadline / due date

• Contact (name, LinkedIn/email)

• Notes (tools, methods, standards, metrics)

• Next action (what & when)

Follow-up rhythm

• T+3 days: polite nudge if no acknowledgement.

• T+10 days: request an update; include a small proof point (e.g., a redacted Pareto or shmoo—no confidential data).

• Post-interview: thank-you within 24 hours referencing one spec requirement & a 30-day quick win.

Shareable Prompt Library (Semiconductor-Specific)

1) Role Decoder

Explain this semiconductor role in plain English: first 90-day deliverables, 3 hardest problems & the exact skills they truly need (tools, methods, standards, metrics). Then list the top 12 CV keywords they’ll search for. [paste spec]

2) Fab/Design Fit Snapshot

From the spec & site notes, infer domain (fab/design/OSAT), key tools (ASML/Lam/AMAT/KLA or Cadence/Synopsys/Mentor), standards (IATF/JEDEC/AEC), and maturity (NPI→ramp). Output a 6-bullet “Why me, why now” pitch.
[spec + brief company notes]

3) CV Bullet Rewriter (Impact-led)

Rewrite these bullets with action+tool/process+metric, mirroring the spec vocab (e.g., ALD conformality, overlay/CDU, HTOL/ESD, UVM/STA, V93000 test time). One line each, UK spelling.
[bullets + spec]

4) Outreach Message (120 words)

Draft a concise message for the hiring contact that references one tool/process/standard from the spec (e.g., ASML overlay or AEC-Q100 quals) & proposes a 30-day quick win. Mirror 3 spec keywords. Confident tone, no fluff.
[spec + company notes]

5) Interview Pack Generator

Produce 8 technical questions + short model answers tailored to this spec (Process/Equipment/Litho/Etch/CMP/Yield/FA/Device/Test/Packaging/EDA/Photonics/Fab SW), plus 5 behavioural questions with STAR hints using my background.
[spec + background]

6) 8D Problem-Solving Pack

Draft an 8D for this defect mode: define problem, interim containment, root cause (tools/data), corrective action, verification, standardisation. Include SPC charts or tests to prove fix.
[defect summary]

7) Offer & Salary Prep (UK)

Given the role & years of experience, suggest a negotiation range in GBP, non-salary levers (training, conference travel, tool access, relocation), & 3 crisp value statements I can use.
[spec + experience]

Keyword & Query Bank (Use Across Alerts, Feeds & Boards)

Titles
Process Engineer, Lithography Engineer, Etch Engineer, Deposition/ALD Engineer, CMP Engineer, Metrology Engineer, Equipment Engineer, Yield/Defect Engineer, Reliability Engineer, Failure Analysis Engineer, Device/Technology Development Engineer, Test Engineer, Product Engineer, Packaging/Assembly Engineer, Quality/APQP/PPAP Engineer, EDA/IC Design Engineer (Digital/Analog/RF), Verification Engineer, Physical Design Engineer, DFT Engineer, Photonics Engineer, MEMS Engineer, Fab Software/APC Engineer.

Tools & Platforms
ASML scanners & tracks, TEL/Lam/AMAT etch/dep, KLA inspection/metrology, CD-SEM, AFM, ellipsometry, Nova/OCD; Advantest/Teradyne ATE; Cadence (Virtuoso/Innovus), Synopsys (DC/PT/ICC2/StarRC), Siemens EDA (Calibre/Tessent); Lumerical/IPKISS; MES (Promis/Camstar), SECS/GEM/Interface-A, E142/E84.

Methods & Standards
SPC/DOE/JMP/Minitab, APC/FDC, 5S/Lean, 8D/5-Whys, JEDEC/AEC-Q100/101, IATF 16949, ISO 9001, ISO 14644, ESD/latch-up, HTOL/HAST/TC, J-STD-020/MSL.

Metrics
Yield/DPPM, scrap, cycle time/WIP, OEE, MTBF/MTTR, overlay/CDU, uniformity, leakage/Rds(on)/Vth, HTOL hours/FIT, UPH/test time, warpage/MSL level.

Modifiers
Remote UK, Hybrid, On-site, Permanent, Contract, Graduate, Internship, Visa sponsorship, Security clearance (SC/DV).

Sample Daily Workflow (7–12 Minutes)

1. Open your alert folder/RSS. Skim titles; bin obvious mismatches.

2. Paste 10–30 items into ChatGPT with your Semiconductor Job Scout prompt.

3. Review the shortlist. Open the top 3–5 high-score roles.

4. Run the deep-dive prompt on your favourite; generate tailored CV bullets & a 120-word cover note.

5. Update your tracker & set deadlines.

6. Apply in one sitting—mirror 6–10 keywords naturally (tools, methods, standards, metrics).

7. Schedule follow-ups immediately.

Consistency beats weekend blitzes.

Troubleshooting & Tuning

“Still getting noise.”
Anchor searches to tool/process tokens (ASML, ALD, OBIRCH, V93000, UVM, Calibre, IATF 16949) and exclude agency spam via -site: or -"recruitment agency".

“Everything looks Senior/Principal.”
Include (Junior OR Associate OR "1–3 years") and exclude (Senior OR Principal OR Lead).

“Remote actually means global.”
Use ("Remote UK" OR "UK-based remote" OR "right to work in the UK") and exclude "anywhere".

“I only want compound semiconductors.”
Bias to SiC, GaN, MOCVD, Epi, AEC-Q101, and include Newport, Cambridge, Sheffield.

“I’m design-only.”
Bias to UVM, STA, P&R, DRC/LVS/PEX, Virtuoso, Spectre, and exclude lithography/CMP/HTOL.

“I want fab software & data.”
Bias to MES, SECS/GEM, Interface-A, FDC/APC, Python/SQL, SPC dashboards.

Lightweight Tracker Template (Copy Text)

Date Found | Role | Company | Location | Link | Cluster | Match (0–100) | Status | Deadline | Contact | Notes (tools/methods/standards/metrics) | Next Action

Status: To apply / Applied / Interview / Offer / On hold / Rejected

Daily command for ChatGPT:
“From my tracker (below), propose today’s top 5 applications, fill missing ‘Next Action’, and draft follow-ups where Status=Applied & T+3 days.”

Copy-Paste Pack (Everything In One Place)

1) Google Alerts seeds

("Process Engineer") (lithography OR etch OR ALD OR CVD OR CMP) (SPC OR DOE) (UK OR "Remote UK")
("Equipment Engineer" OR maintenance) (vacuum OR plasma OR "RF generator" OR EFEM) (SECS/GEM OR PLC) (UK OR "Remote UK")
("Yield Engineer" OR "Reliability Engineer" OR "Failure Analysis") (HTOL OR HAST OR OBIRCH OR FIB OR AEC-Q100) (UK OR "Remote UK")
("Device Engineer" OR "Technology Development") (TCAD OR Sentaurus OR Silvaco OR "WAT" OR epi) (UK OR "Remote UK")
("Test Engineer" OR "Product Engineer") (Advantest OR Teradyne OR DFT OR JTAG OR "test program") (UK OR "Remote UK")
("Packaging" OR OSAT OR "flip-chip" OR WLCSP OR FOWLP OR "wire bond") (JEDEC OR "J-STD-020" OR MSL) (UK OR "Remote UK")
("Digital Design" OR "Analog IC" OR "Verification" OR "Physical Design") (UVM OR PrimeTime OR Innovus OR Virtuoso OR Calibre) (UK OR "Remote UK")
("Silicon Photonics" OR MEMS) (Lumerical OR IPKISS OR DRIE OR "wafer bonding") (UK OR "Remote UK")
("MES" OR "SECS/GEM" OR "Interface A" OR "FDC" OR "APC") (Promis OR Camstar OR E142 OR E84 OR Python OR SQL) (UK OR "Remote UK")
("Graduate" OR "Junior" OR "Internship") (semiconductor OR lithography OR "IC design" OR photonics OR MEMS) (UK OR "Remote UK")

2) ATS-focused Google search

(semiconductor OR "IC design" OR "wafer fab" OR photonics OR MEMS)
(site:boards.greenhouse.io OR site:lever.co OR site:workable.com OR site:ashbyhq.com OR site:smartrecruiters.com OR site:icims.com OR site:successfactors.com)
(UK OR "Remote UK")

3) Academic search

("semiconductor" OR photonics OR MEMS) (postdoc OR "research fellow" OR "research engineer")
(site:jobs.ac.uk OR site:cam.ac.uk OR site:ox.ac.uk OR site:ed.ac.uk OR site:imperial.ac.uk)
(UK)

4) Semiconductor Job Scout (short version)

You are my UK Semiconductor Job Scout. From pasted listings, remove duplicates, rank by fit to my criteria, and output:
• Summary (counts + scoring)
• Top 10 roles (Title — Company — Location — Link — Score — 1-line why)
• Per-role actions (3 CV bullets, 6–10 keywords, 3-sentence outreach)
Criteria: [paste your clusters & must-haves]

5) Deep-dive tailoring

Analyse this spec. Return: 3 tailored CV bullets (action+tool/process+impact), 10 keywords, a 120-word cover note referencing one tool/process/standard & a 30-day quick win, and 6 interview Qs with model answers.
Spec: [paste]  |  Background: [paste]

6) Follow-up message

Please draft a concise follow-up for my application submitted on [date], referencing [one tool/process/standard/metric] from the spec and reaffirming my fit in 2 sentences.

Final Thoughts

Your edge in semiconductor job-hunting isn’t heroic scrolling—it’s a repeatable pipeline. Put discovery on autopilot with alerts & RSS, let ChatGPT act as your Semiconductor Job Scout, and ship one excellent application per day. Mirror the tools, methods, standards and metrics the spec cares about (from ASML overlay/CDU to V93000 test time or UVM/STA closure). Quantify improvements in yield, DPPM, cycle time, MTBF/MTTR, UPH and reliability. Keep tight feedback loops—and you’ll feel the shift from hunting posts to booking interviews across the UK’s most exciting fabs, design houses and photonics/MEMS teams.