Semiconductor Jobs

Analog Devices · Edinburgh

Lead verification of complex mixed-signal ICs across the full development cycle, from concept and verification planning through implementation, execution and release. Develop UVM and formal testbench architectures, define coverage and closure metrics, debug gate-level simulations, and mentor junior engineers while leading IP or SoC verification efforts.

Semtech · Bristol

Architect test strategies for high-speed mixed-signal and RF SiGe products, from first silicon to mass production, covering 200Gbps+ SerDes, CDRs and signal conditioning. Sets DFT and testability standards, builds reusable test IP, and leads NPI transfers to high-volume OSATs while mentoring engineers.

Semtech · Bristol

Graduate role validating next-generation high-speed semiconductor devices, working hands-on in the lab from week one. You'll build test automation in Python or LabVIEW, take measurements on components running at 10Gbit/s and above, and learn high-speed signal integrity with Altium PCB tools. Based in Bristol, hybrid with four days in office.

Analog Devices · Hayes

Field Application Engineer supporting regional accounts across the UK, working with Account Managers and Business Unit specialists to solve complex application-level problems and drive design wins. Involves building customer relationships, identifying new business opportunities, training customers and presenting at seminars, with around 10% travel.

Renesas Electronics · Edinburgh

Owns the full analog and mixed-signal development cycle for IC products, from specification and system architecture through IP requirements, verification planning and layout. Works with product definition, marketing, project management and cross-functional test, product engineering and quality teams, and mentors team members. Requires precision analog, power management and high-voltage BCD design expertise.

Renesas Electronics · Edinburgh

Lead the design and verification of CMOS analog blocks for custom mixed-signal ASICs, taking technical ownership of full-chip or major system-level blocks from specification through to production ramp. The role combines hands-on circuit design with mentoring a team of engineers, working alongside digital, layout, DFT and test teams, and driving silicon debug and characterisation.

Teledyne FLIR · Chelmsford

Hands-on role spanning clean-room and office work, owning verification and test across space and science imaging detector projects. You define test flows, commission and script EGSE/OGSE/MGSE equipment, run functional, electrical, mechanical and environmental campaigns to ECSS standards, and train operations staff. Works closely with project, product assurance and manufacturing teams.

University of Surrey · Guildford · £38,448 – £46,970 pa

Develops and validates predictive models of source-gated and multimodal transistors on an EPSRC project, using TCAD, compact modelling, surrogate modelling or physics-informed machine learning. Works closely with experimental researchers to fit models against measured data and inform device and circuit design, producing publications and reusable simulation frameworks.

The University of Manchester · Manchester · £21,805 pa

A 3.5-year funded PhD designing a Smart Network-on-Chip, an asynchronous communication fabric with intelligence built into its microarchitecture, to manage congestion in 2.5D chiplet systems. The work replaces static routing heuristics with data-driven, learning-based policies, building on an existing RTL-verified asynchronous NoC IP, with possible directions in lightweight inference engines and distributed adaptive traffic management.

Reperio Human Capital · Cork, Ireland · £103,589 – £129,486 pa

Lead and grow a verification team while remaining hands-on with mixed-signal power ICs. You define verification strategy, methodology and sign-off criteria, architect UVM/SystemVerilog environments at block, subsystem and SoC level, and own verification plans, regressions and coverage closure. Works closely with design, firmware, applications and test teams, with three days a week on site in Cork.

Forefront RF · Cambridge

Owns and develops the Quality Management System to ISO 9001 standards, establishing scalable quality and reliability processes for new product introduction, qualification and manufacturing ramp. Leads reliability testing, failure analysis and root cause investigations while managing quality relationships with foundries, OSATs and test providers, and supports customer qualification requirements.

Cambridge GaN Devices · Cambridge

Senior leadership role owning the packaging function for GaN power semiconductors, combining people leadership with hands-on design of wirebond, flip chip and embedded packages. Involves multiphysics simulation, supplier development, qualification testing and roadmap input, working with internal teams and overseas partners from the Cambridge office.

Graphcore · Bristol · £45,000 pa

Two-year graduate programme rotating through manufacturing operations teams focused on product test, supporting silicon package assembly, PCBA production, component selection and BoM management. You'll analyse manufacturing and product performance data, investigate issues and help shape tests, working with colleagues in the UK, Taiwan and India.

Graphcore · Bristol · £2,500 pm

A 12-week summer internship in the Product Test and Diagnosis team within Manufacturing Operations, working hands-on with advanced AI hardware across silicon, boards, server blades or rack-scale systems. You'll develop automated test solutions, run system-level tests and analyse results, connecting manufacturing test to design, validation and performance.

University of Warwick · Coventry · £21,805 pa

Develops medium-voltage solid-state transformer cells for hyperscale AI data centres and net-zero grids, tackling high-frequency power conversion, compact magnetic links and electrical-thermal degradation under high-dv/dt stress. Combines multi-physics finite-element modelling in ANSYS/COMSOL with experimental validation in a high-voltage power electronics lab, culminating in a scaled hardware prototype.