Semiconductor Jobs

• Cambridge
• On-site
• £45,000 – £55,000 pa
• Mid-level

Own significant blocks of RTL from specification through implementation, verification and into working hardware, focused on physical layer design in the communications space. Work alongside senior and principal engineers on digital RF and fixed-point DSP, with hands-on lab time on AMD/Xilinx FPGA platforms. A new role in a small, established team with low attrition.

AMD · Xilinx · MATLAB

• Edinburgh
• Senior

Implements and verifies digital logic for mixed-signal SoCs used in high-performance power systems, covering RTL development, synthesis, static timing analysis and DFT insertion. Works with analog, firmware and validation teams on integration, silicon bring-up and lab debug, with scope to improve methodology and automation.

Genus · Innovus · Tempus +4

• Portsmouth
• Hybrid · 1–2 days in office
• £82 ph
• Mid-level
• Contract

Designs production-ready digital electronics, covering component selection, simulation, schematic capture and PCB layout guidance. Develops FPGA/CPLD solutions in VHDL and verifies designs through simulation, analysis and test, including EMC and system bring-up. Works within a multi-disciplinary Mission Systems team on defence electronics, supporting peer and formal design reviews.

FPGA · CPLD · VHDL +4

• Edinburgh
• Hybrid · 3 days in office
• Senior
• Permanent

Owns verification of complex digital and mixed-signal ASIC designs, building SystemVerilog/UVM testbenches and running block-level to full-chip simulation, coverage and regression. Includes gate-level simulation with SDF timing annotation and mentoring junior engineers. Hybrid role with three set office days in Edinburgh.

Synopsys VCS · Cadence Xcelium · Tcl +4

• Edinburgh
• Entry level
• Internship

Join a Consumer Audio design team in Edinburgh to work on real mixed-signal IC development, from circuit architecture research and feasibility studies to transistor-level design, simulation and verification of analog blocks. You will build testbenches, analyse trade-offs around noise, distortion and power, and collaborate with layout engineers through physical implementation and design reviews.

Cadence Virtuoso · Spectre · MATLAB +3

• Coventry
• Hybrid
• £40,000 – £60,000 pa
• Mid-level
• Permanent

Work across the full FPGA design cycle, from requirements analysis and specification through RTL design, implementation and verification. Define module architectures, run synthesis and timing analysis, and integrate FPGAs into target hardware, using VHDL or Verilog and leading vendor tools alongside senior engineers and system architects.

• Whitstable
• On-site
• Mid-level
• Permanent

Hands-on FPGA design role covering the full development lifecycle, from requirements and VHDL design through simulation, verification, synthesis, timing closure and hardware testing. You'll work in a small, cross-disciplinary team on advanced electronic systems for high-reliability applications, with genuine ownership of designs and input into product release.

AMD · Xilinx · Intel +7

• Bristol

Integrate IP and subsystems into top-level SoC designs, maintaining build and configuration environments while running synthesis, linting, CDC/RDC and timing checks. Work closely with verification and physical design teams on clean interface hand-offs, debug integration issues across hierarchies, and improve automation flows using Python, Tcl, SystemVerilog or VHDL.

SystemVerilog · VHDL · Python +1

• Stevenage
• Hybrid
• £85 – £90 ph
• Mid-level
• Contract

Design and verify complex FPGA architectures for defence and security systems, working across the full lifecycle with VHDL, Simulink and SystemVerilog/UVM testbenches. Targets Xilinx, Intel and Microsemi devices, using QuestaSim/ModelSim and low-level C for embedded integration within a multidisciplinary team.

Xilinx · Intel · Microsemi +3

• Bristol
• Remote
• £50 – £60 ph
• Senior

Verification of a next-generation multi-die SoC, covering subsystem- and SoC-level functional verification with SystemVerilog/UVM and processor-driven C test programs on embedded cores. Involves adapting existing UVM environments, debugging RTL simulation failures, running regressions and driving functional coverage closure, with scripting in Python, Perl or shell.

SystemVerilog · UVM · ARM +3

• United Kingdom
• £300 – £600 pd

Hands-on verification role covering subsystem and SoC functional verification, reusing and enhancing System Verilog/UVM testbenches, and developing processor-based C tests. The engineer runs regressions, debugs complex RTL simulation failures with waveform tools, and drives functional coverage closure while collaborating on verification planning.

SystemVerilog · UVM · Python +2

• Oxford
• £80,000 – £120,000 pa
• Lead

Lead the architecture and full lifecycle delivery of high-throughput FPGA subsystems for next-generation medical device platforms, from requirements through RTL implementation, ASIC bring-up and lab validation. The role combines hands-on SystemVerilog/Verilog design using AMD/Xilinx toolchains with technical leadership, mentoring mid/senior engineers and championing CI/CD automation.

AMD · Xilinx · Vivado +3

• Edinburgh
• Hybrid
• Lead
• Permanent

Provide technical leadership for a global engineering compute and design-data-management environment, combining hands-on CAD work with infrastructure ownership. You will own Perforce Helix and IPLM methodologies, build Python and shell automation, and guide migration from legacy data platforms. The role spans Linux compute environments, EDA tool configuration, documentation and training across distributed semiconductor teams.

Perforce Helix · Methodics IPLM · Cadence Virtuoso +4

• Edinburgh
• Lead

Develops verification and emulation environments for complex Chiplet designs, building UVM-SV scoreboards, functional coverage, and SystemVerilog assertions for formal and simulation. Integrates Cadence VIP and accelerated VIP, manages vPlans in vManager, and maintains automated regression environments using Jenkins and GIT within an experienced Chiplet team.

Cadence Palladium · Cadence VIP · Cadence vManager +3

• Whiteley
• £50,000 – £80,000 pa
• Senior

Design and optimise capacitive sensing architectures, develop and verify RTL in Verilog/SystemVerilog, and write embedded C/C++ software for sensing and signal processing. Lead silicon bring-up, debugging and validation across analogue, digital and firmware domains, collaborating with global teams on HMI solutions.

Verilog · SystemVerilog · C/C++ +7