Semiconductor Jobs

• Bristol

Hands-on lab role validating and debugging memory and system interfaces on advanced AI compute hardware, focusing on LPDDR5-9600, slow-speed interfaces, PCB issues, power behaviour and signal integrity. You own board bring-up, root cause analysis and memory subsystem tuning, working closely with architecture, silicon, firmware and PCB design teams.

LPDDR5-9600 · Oscilloscopes · BERT +2

• Bristol
• £45,000 pa
• Entry level
• Permanent

Two-year graduate programme spanning Hardware Design and Signal Integrity on the electronic systems behind AI compute platforms. You'll develop circuits, schematics and PCB layouts, or analyse PCIe, Ethernet and DDR interfaces using simulation tools like Mentor Expedition, Ansys HFSS and Keysight ADS, comparing models with lab measurements.

Mentor Expedition · Ansys HFSS · Keysight ADS +3

• Oxford
• Hybrid
• Senior

Architect and maintain UVM/SystemVerilog verification environments for complex FPGA designs, defining verification plans with constrained-random testing and functional coverage. Build automated regression suites and CI pipelines, collaborating with RTL engineers to debug and ensure reliable quantum control systems.

SystemVerilog · UVM · Python

• Fareham
• Hybrid · 3 days in office
• £70,000 – £75,000 pa
• Senior
• Permanent

Support the integration of semiconductor products into customer devices, testing internal developments and providing direct technical support for design-in activities. Design and build hardware tooling, coordinate project tasks, and act as a technical interface to customers, including international travel. The role also carries technical leadership across multiple teams, mentoring engineers and driving autonomous development.

• Didcot
• Hybrid · 4 days in office
• £41,414 – £58,679 pa
• Senior
• Contract

Develop and maintain HDL firmware for Xilinx FPGAs in Vivado, implementing feedback control, filtering and interlock handling with state machines for magnet power supply controllers. The role covers simulation, verification and on-hardware validation using logic analysers, plus Ethernet-based control interfaces, within a not-for-profit scientific organisation on a major facility upgrade.

Xilinx · Vivado · ADC +7

• Bedford
• On-site
• £43,000 – £55,000 pa
• Senior

Take mixed electrical and electronic designs from concept to completion within a structured phase-gate process, covering analogue, digital, microprocessor and FPGA design, power electronics, simulation, test and PCB layout. Work on defence and aerospace hardware for harsh environments, using Altium, JTAG debug and Windchill, with ownership of processes, supplier reviews and compliance documentation.

Altium · Windchill · PLM +1

• Cambridge
• On-site
• Lead
• Permanent

Hands-on technical lead for RF subsystem design, simulation and validation, covering circuits such as LNAs, PAs, filters and duplexers. Owns performance, quality and delivery against system architecture, runs design reviews and verification (S-parameters, NF, phase noise, EVM, ACPR), and mentors RF engineers while working with the System Architect and manufacturing teams.

• Cambridge
• On-site
• Permanent

Hands-on role driving semiconductor assembly and packaging for RF products, working with OSATs and manufacturing partners on process development. Supports new product introduction, yield improvement, root-cause analysis, reliability testing and qualification, and maintains assembly documentation and process flows. Newly created position shaping the transition from prototype to volume production.

OSAT

• Cambridge
• Mid-level

Designs and develops FPGA firmware for defence technologies spanning communications, sensors and detection systems, working within a small multidisciplinary engineering team. Uses VHDL or Verilog and collaborates with internal teams and external groups, with security clearance required and room to grow as the company expands.

• Durham
• On-site
• Senior

Support 300mm wafer fabs by introducing new process technology, ramping yield and providing RMA support. Monitor electrical performance, SPC and OOC parameters, run DOEs and drive defect characterisation and root-cause analysis. Work closely with process integration, principal engineers and cross-functional teams on high-volume manufacturing.

JMP · 300mm Wafer Fab · SPC +3

• Durham
• Senior

Lead the development, qualification and transfer of back-end semiconductor assembly processes into high-volume manufacturing, with particular focus on laser processing, die singulation, wafer-on-frame debonding and advanced packaging. Design and execute DOEs, set process windows and control plans, and mentor engineers while supporting new product introductions and customer-driven transfers.

JMP · Minitab · Excel

• Fareham
• £55,000 – £65,000 pa
• Senior

Lead algorithm development for RISC-V-based capacitive touch controllers, owning projects from problem definition and modelling through experimentation, optimisation and validation on real hardware. Work spans sensor physics, mixed-signal electronics and DSP, designing filtering, calibration and noise-rejection algorithms while mentoring junior colleagues.

MATLAB · Python · RISC-V +5

• Bristol
• Remote
• Lead

Customer-facing technical strategist driving design wins for high-speed analog ICs (drivers, TIAs, copper redrivers) with Tier 1 hyperscalers and EMEA optical accounts. Leads co-development of 1.6T/3.2T interconnect, signal integrity and transceiver validation, while also supporting PON and Mobile Transport accounts and influencing product roadmaps.

IEEE 802.3 · OIF · ITU-T PON +7

• Didcot
• Hybrid · 4 days in office
• £41,414 – £67,481 pa
• Senior
• Contract

Develop and debug HDL firmware for Xilinx FPGAs in Vivado, implementing full-cycle designs for magnet power supplies on the Diamond-II upgrade, including feedback control, filtering and interlock state machines. Work with ADCs, DACs, memory and microcontrollers, verifying designs via simulation and on-hardware testing, and collaborate with hardware and control engineers on Ethernet-based interfaces.

Xilinx · Vivado · MATLAB +7

• Derby
• On-site
• £55,000 – £60,000 pa
• Mid-level
• Permanent

Contribute across the FPGA development lifecycle, from system and module design to verification and documentation, reporting to the Head of FPGA Development. Work with VHDL, SoC technologies, simulation tools like Riviera Pro or QuestaSim, and scripting in TCL within a multidisciplinary engineering team. The role evolves with the company's technologies and may involve UK travel between sites.

Riviera Pro · QuestaSim