Senior FPGA Engineer - Compute Architecture
Redline Group Devizes £80,000 – £90,000 pa
Translate probabilistic algorithms from Python, C++, MATLAB and pseudocode into pipelined, resource-efficient FPGA RTL, writing custom VHDL from scratch where vendor IP is unsuitable. Architect high-speed data acquisition pipelines using ultra-fast ADCs, PCIe, Ethernet and transceivers, and handle verification, bring-up and timing/power optimisation across multiple clock domains alongside hardware, software, research and ASIC teams.