Semiconductor Jobs

16 jobs for “Process Engineer”

Results

Principal Process Engineer - Metal-Oxide PVD

Last month

Pragmatic Semiconductor Durham

Owns metal-oxide PVD process development, qualification and sustaining on 300mm production tools, defining process windows and driving SPC, Cpk and root-cause investigations for yield-limiting film issues. Combines deep technical leadership of reactive sputtering with line management of a small deposition team, partnering with equipment, integration and reliability engineers.

On-site

Junior Process Engineer

Last week

Bluegate Consulting Oldham

Assist with semiconductor manufacturing in a growing Oldham facility, controlling process performance, maintaining efficient workflow and implementing improvements. Requires hands-on front-end process knowledge, SPC and a degree in electronics, aimed at someone early in their career.

Principal Advanced Packaging Engineer (R&D)

Last week

Pragmatic Semiconductor Stockton-on-Tees

Lead the technical development of FlexIC wafer-level packaging, chip-scale packaging, die attachment and system-in-package integration, setting technical direction and selecting materials, processes and partners. Drive the internal roadmap with Product Management, Engineering and Operations, validating scalable processes and transferring them to production teams. A newly created principal-level role spanning R&D, reliability qualification and external development partners.

Electrical Engineer

2 weeks ago

Gold Group Bedford £54 – £64 ph

Lead the design, development and support of mixed electrical/electronic LRU solutions from concept to completion through a phase-gate process, including analogue, digital, microprocessor and FPGA circuitry, schematic capture and PCB layout. The role provides technical governance to the team, reviews supplier capabilities and produces documentation, working on-site two mandatory days a week.

Hybrid Contract Clearance Required

Junior Embedded Engineer (RTOS)

5 months ago

Lumai Oxford

Builds firmware, peripheral drivers and RTOS-based control software for an optical AI accelerator, covering RTOS tasks and IPC, board support package bring-up, boot loaders and first-boot debugging on custom hardware. Works closely with a senior embedded engineer and hardware teams, writing unit and integration tests and maintaining embedded CI pipelines.

Hybrid Permanent

Get new Process Engineer roles by email. One email a morning when new roles match. Stop any time. Alerts don't use filters, so you'll hear about every role for this search, not just Junior, Lead, Director.

Lead Production Engineer

2 weeks ago

Teledyne FLIR UK - Lincoln

Drive value stream and production method improvements to boost throughput and manufacturing capacity, support product ramp-ups and New Product Introduction, and improve manufacturing and test processes to raise yield and cut costs. Lead root cause investigations and corrective actions, and identify automation and tooling opportunities for future growth.

Principal Engineer, Design Verification

12 months ago

Analog Devices Edinburgh

Lead verification of complex mixed-signal ICs across the full development cycle, from concept and verification planning through implementation, execution and release. Develop UVM and formal testbench architectures, define coverage and closure metrics, debug gate-level simulations, and mentor junior engineers while leading IP or SoC verification efforts.

Hybrid Permanent Clearance Required

Principal EDA Engineer

Last week

Renesas Electronics Edinburgh

Provide technical leadership for a global engineering compute and design-data-management environment, combining hands-on CAD work with infrastructure ownership. You will own Perforce Helix and IPLM methodologies, build Python and shell automation, and guide migration from legacy data platforms. The role spans Linux compute environments, EDA tool configuration, documentation and training across distributed semiconductor teams.

Hybrid Permanent

Principal EDA Engineer

Last week

Renesas Electronics Swindon

Provide technical leadership for a global engineering compute and design-data-management environment, combining hands-on CAD work with Perforce Helix and IPLM-based data management. You will develop Linux-based engineering environments, Python and shell automation, project/workspace methodologies, and migration paths from legacy platforms, while supporting EDA tool integration and training engineering teams.

Hybrid Permanent

Manager - Analog IC Design

3 weeks ago

Semtech Bristol

Lead a Bristol team of analog IC design engineers, spanning associate to senior level, with direct oversight of performance, development and recruitment. The role is hands-on, guiding complex design work while managing project schedules, budgets and cross-functional priorities for optical communications ICs such as laser drivers, TIAs and transceivers.

Hybrid

Grid Insights Architect

Last month

Analog Devices Edinburgh

Hands-on principal-level role owning the design and development of signal processing and machine learning algorithms for power system monitoring, asset health and grid analytics. Work spans the full pipeline from modelling and simulation to deployment across edge-to-cloud and embedded platforms, collaborating with hardware, firmware and data teams and engaging utilities and grid equipment OEMs. Includes mentoring engineers with a pathway to broader technical leadership.

Clearance Required
Cambridge GaN Devices logo

Director of Packaging

2 months ago

Cambridge GaN Devices Cambridge

Senior leadership role owning the packaging function for GaN power semiconductors, combining people leadership with hands-on design of wirebond, flip chip and embedded packages. Involves multiphysics simulation, supplier development, qualification testing and roadmap input, working with internal teams and overseas partners from the Cambridge office.

On-site Permanent

Lead Software Engineer

17 months ago

Cadence Newcastle upon Tyne

Develops and maintains a C++ codebase for next-generation EDA tools, focusing on computational geometry, geometry manipulation and algorithmic complexity for sub-20nm IC design. Involves writing design, function and test specifications, interfacing with build and regression systems, and collaborating with a global cross-functional team.