29 jobs for “Process Engineer”
Pragmatic Semiconductor Durham
Support 300mm wafer fabs by introducing new process technology, ramping yield and providing RMA support. Monitor electrical performance, SPC and OOC parameters, run DOEs and drive defect characterisation and root-cause analysis. Work closely with process integration, principal engineers and cross-functional teams on high-volume manufacturing.
Enterprise Recruitment Towcester £60,000 – £65,000 pa
This role involves hands-on engineering support for production operations, maintaining and improving epitaxy equipment, and driving continuous improvement initiatives. You will coordinate maintenance, support equipment upgrades, and collaborate with cross-functional teams to ensure high equipment uptime and compliance with safety standards.
Beautiful Recruitment Northamptonshire
Provide equipment engineering leadership in a UK wafer fab, covering advanced fault-finding, preventative maintenance and optimisation of semiconductor process tools handling hazardous chemicals and speciality gases. Mentor technicians and junior engineers, manage vendors and contractors, and drive TPM and 8-step improvement projects while reporting OEE metrics to executives.
Semtech Sevenoaks CA$95,000 – CA$122,000 pa
Owns new product introduction for high-speed analog and mixed-signal ICs, from concept through volume manufacturing and end-of-life. Defines DfT/DfM requirements, drives ATE test program development, PVT characterisation, ATE-to-bench correlation, yield analysis and DOE-based optimisation. Works cross-functionally with design, test, quality and operations, and mentors junior engineers.
Belcan Newport £85 ph
Owns the full FPGA development lifecycle on a defence and aerospace programme, from requirements capture and architecture through VHDL implementation, verification and integration onto target hardware. Also leads and mentors other engineers, manages work packages to cost and quality targets, and reports progress to engineering leadership. Based fully on-site in Newport under SC clearance.
Morson Edge Spalding £60 – £90 ph
Deliver FPGA firmware for defence, transportation and aerospace products, covering architecture, requirements, design, verification and validation. Work alongside systems, software and hardware engineers using VHDL, SystemVerilog, C++ and tools such as ModelSim/QuestaSim, with a mix of on-site and remote working plus customer site visits.
Analog Devices Newbury
Field Applications Engineer role focused on system-level engagement with Aerospace, Defense and Communications customers at ADI's Newbury Catalyst site. You will develop and execute pilot demos using evaluation boards, system platforms and COTS modules, write Python code to tailor solutions, and work on-site with customers customising radar, electronic warfare and sensing designs. Part of the wider European System Platforms team, feeding customer insights back into future ADI products.
Belcan Newport £85 ph
Design, develop and verify FPGA solutions in VHDL across the full development lifecycle, from requirements capture and architecture definition to simulation, validation and hardware integration. You'll provide technical leadership within a multidisciplinary team on a Defence & Aerospace programme, using Xilinx, Altera or Microsemi devices with Vivado, Quartus II, ModelSim or Libero tooling.
Lumai Oxford
Owns dense, high-layer-count PCB layout from schematic handoff to fabrication release, covering stackups, HDI structures, controlled-impedance routing, differential pairs and BGA breakout for large FPGAs and custom ASICs. Acts as the main technical contact with fabricators and assembly houses, and sets the footprint libraries, design rules and CAD standards the wider team works to.
Endeavour Recruitment Bedford £43,500 – £54,500 pa
Design and develop mixed electrical/electronic solutions from concept to completion, including analogue, digital, microprocessor, FPGA and power electronics for harsh environments. Based on-site at Ampthill, reporting to the Design Team Lead, the role covers circuit simulation, EMC awareness, testing and technical documentation within a phase-gate process.
Semtech Bristol
Lead bench PVT characterization for high-speed optical and electrical signal integrity products, developing automated test environments and analyzing complex datasets. Work with an international team across the UK, Canada, US and Mexico, using Python automation and mentoring junior engineers in a lab-based NPI role.
Analog Devices Edinburgh
Join a collaborative Edinburgh team developing low-power analog and power-management IP for highly integrated mixed-signal ICs. The intern contributes to architecture, transistor-level design, simulation and verification of DC/DC converter IP such as buck, boost and buck-boost topologies, including analog sub-circuits like error amplifiers, comparators and gate drivers. Work spans behavioural modelling, layout review and potentially laboratory silicon evaluation.
IonQ Oxford
Owns the full lifecycle of electrical reliability fixes on operational trapped-ion quantum computers, from triaging and root-causing control and drive-electronics faults to designing, prototyping and retrofitting permanent solutions. Works across Operations, Science and Manufacturing on fleet-wide upgrades, standardising hardware and building telemetry to reduce downtime.
IonQ Oxford
Integrate all features needed to operate quantum computers into complex multi-layer ion-trapping chips, guiding designs from requirements through layout and tape-out. Work closely with scientists and fabrication engineers on metal-track routing and photonics/CMOS interfaces, using GDSFactory in Python and Cadence. Hybrid role, three days per week in the Oxford office.
Lumai Oxford
Owns signal and power integrity across high-speed boards and packages, running pre-layout channel studies, post-layout SI analysis with IBIS-AMI models, and PDN impedance and DC drop work for high-current ASIC and FPGA rails. Channels span chip, package, interposer, board and optical engine, with heavy bench correlation using VNAs, TDRs and oscilloscopes to feed design rules.
