Semiconductor Jobs

Analog Devices · Edinburgh

Implements and verifies digital logic for mixed-signal SoCs used in high-performance power systems, covering RTL development, synthesis, static timing analysis and DFT insertion. Works with analog, firmware and validation teams on integration, silicon bring-up and lab debug, with scope to improve methodology and automation.

Analog Devices · Newbury

Lead the architecture and transistor-level design of mixed-signal ICs such as ADCs, DACs, PLLs and SerDes PHY subsystems for advanced FinFET SoC products. The role sits in the Advanced Cores Group, combining architectural decision-making, design reviews, layout and test guidance with mentoring of junior engineers.

Semtech · Sevenoaks · CA$95,000 – CA$122,000 pa

Owns new product introduction for high-speed analog and mixed-signal ICs, from concept through volume manufacturing and end-of-life. Defines DfT/DfM requirements, drives ATE test program development, PVT characterisation, ATE-to-bench correlation, yield analysis and DOE-based optimisation. Works cross-functionally with design, test, quality and operations, and mentors junior engineers.

Semtech · Bristol

Our TeamSemtech's New Product Introduction (NPI) Product Engineering Team is the central engineering function behind every new product we bring to market. Our team of focused and talented engineers takes full ownership of new product development — driving each program...

Renesas Electronics · Edinburgh

Design and verify CMOS analog blocks such as amplifiers, oscillators, LDOs, comparators and reference/biasing circuits for custom ASICs, balancing performance, area, power and timescale. The role carries technical leadership of sub-systems from specification through to production ramp, guiding layout, DFT and test engineers, driving silicon debug and lab evaluation, and mentoring less experienced team members.

Wolviston Management Services · Newton Aycliffe

Generates, verifies and releases MMIC integrated circuit layouts and mask reticle designs within a Design Services team, taking designs from concept through to mask release. Liaises with customers, engineers, programme managers and external mask manufacturers, and maintains reticle records and design archives. Uses CAD layout tools such as KLayout, L-Edit or Nazca Design.

Wolviston Management Services · Newton Aycliffe

Generates, verifies and releases MMIC integrated circuit layouts and mask reticle designs, taking them from initial concept through to mask release. Works in a Design Services team, producing mask order documentation and reticle records while liaising with engineers, programme managers, customers and external mask manufacturers.

Redline Group · Glasgow · £80,000 – £110,000 pa

Lead a multi-disciplinary team of up to 100 people, driving pure NPI development for next-generation semiconductor products. Responsibilities include creating project proposals, presenting to customers, providing technical leadership across hardware, software and mechanical teams, and managing project schedules, budgets and resource allocation. Works closely with the General Manager on complex, electronically biased product development.

Cambridge GaN Devices · Cambridge

Define and architect test hardware for GaN power devices and ICs, covering fixtures, sockets, probing, switching and multi-site parallel setups for static, dynamic and mixed-signal measurements. Lead test hardware workstreams from concept to release, write specifications, review designs, and mentor engineers while shaping the test equipment roadmap.

Renesas Electronics · Bourne End

Defines and drives product security strategy across Renesas MCU and MPU platforms, working with product divisions, software teams and ecosystem partners from architecture design to deployment. Represents the company in industry standards bodies and leads compliance with frameworks such as CRA, RED, IEC 62443, SESIP, PSA Certified and FIPS 140-3.

University of Surrey · Guildford · £38,448 – £46,970 pa

Develops and validates predictive models of source-gated and multimodal transistors on an EPSRC project, using TCAD, compact modelling, surrogate modelling or physics-informed machine learning. Works closely with experimental researchers to fit models against measured data and inform device and circuit design, producing publications and reusable simulation frameworks.

The University of Manchester · Manchester · £21,805 pa

A 3.5-year funded PhD designing a Smart Network-on-Chip, an asynchronous communication fabric with intelligence built into its microarchitecture, to manage congestion in 2.5D chiplet systems. The work replaces static routing heuristics with data-driven, learning-based policies, building on an existing RTL-verified asynchronous NoC IP, with possible directions in lightweight inference engines and distributed adaptive traffic management.

Reperio Human Capital · Cork, Ireland · £103,589 – £129,486 pa

Lead and grow a verification team while remaining hands-on with mixed-signal power ICs. You define verification strategy, methodology and sign-off criteria, architect UVM/SystemVerilog environments at block, subsystem and SoC level, and own verification plans, regressions and coverage closure. Works closely with design, firmware, applications and test teams, with three days a week on site in Cork.

Forefront RF · Cambridge

Owns and develops the Quality Management System to ISO 9001 standards, establishing scalable quality and reliability processes for new product introduction, qualification and manufacturing ramp. Leads reliability testing, failure analysis and root cause investigations while managing quality relationships with foundries, OSATs and test providers, and supports customer qualification requirements.

University of Warwick · Coventry · £21,805 pa

Develops medium-voltage solid-state transformer cells for hyperscale AI data centres and net-zero grids, tackling high-frequency power conversion, compact magnetic links and electrical-thermal degradation under high-dv/dt stress. Combines multi-physics finite-element modelling in ANSYS/COMSOL with experimental validation in a high-voltage power electronics lab, culminating in a scaled hardware prototype.