IonQ Oxford
This role involves leading the validation and characterisation of analogue and mixed-signal ASICs for trapped-ion quantum processors. Responsibilities include test planning, platform development, first-silicon bring-up, and system integration, with a focus on cryogenic testing and reusable automation.
Cambridge GaN Devices Cambridge
Design GaN power ICs and Si gate drivers using EDA tools, covering schematic capture, RTL, analog/digital and mixed-signal simulation, synthesis, STA, PNR and AMS verification. Also develops test solutions, analyses wafer-level and packaged device data, documents designs, debugs ICs and generates IP for patent applications within a growing R&D engineering team.
Cambridge GaN Devices Cambridge
Senior leadership role owning the packaging function for GaN power semiconductors, combining people leadership with hands-on design of wirebond, flip chip and embedded packages. Involves multiphysics simulation, supplier development, qualification testing and roadmap input, working with internal teams and overseas partners from the Cambridge office.
IonQ Oxford
Owns the full lifecycle of electrical reliability fixes on operational trapped-ion quantum computers, from triaging and root-causing control and drive-electronics faults to designing, prototyping and retrofitting permanent solutions. Works across Operations, Science and Manufacturing on fleet-wide upgrades, standardising hardware and building telemetry to reduce downtime.
IonQ Oxford
Integrate all features needed to operate quantum computers into complex multi-layer ion-trapping chips, guiding designs from requirements through layout and tape-out. Work closely with scientists and fabrication engineers on metal-track routing and photonics/CMOS interfaces, using GDSFactory in Python and Cadence. Hybrid role, three days per week in the Oxford office.
