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This role involves designing and integrating analog/mixed-signal circuits for advanced semiconductor packaging and heterogeneous integration. Responsibilities include PHY-level interfaces, custom pad circuits, and working with industry partners to develop and commercialize innovative solutions.
The Senior QPU Design Engineer will integrate features into complex chips for quantum computers, collaborating with scientists and fabrication engineers. Responsibilities include chip layout, multi-layer design, and project ownership.
Develop and debug ATE test programs for an advanced AI accelerator chip, covering digital logic, memory, and high-speed interfaces. Perform silicon bring-up, characterization, and failure analysis while collaborating with design and DFT teams. Support high-volume manufacturing ramp and advanced packaging test flows.
Lead the development and execution of manufacturing test strategies for an advanced AI accelerator chip, overseeing both internal teams and external partners. Drive test architecture, DFT integration, and silicon bring-up across high-speed interfaces like PCIe Gen6 and LPDDR, with a focus on yield, scalability, and advanced packaging. Work closely with cross-functional teams to ensure robust test coverage and successful high-volume manufacturing transfer.
The Senior Electronics Engineer will work on root-causing, designing, and deploying electronics system design fixes for IonQ's quantum computers. Responsibilities include triaging issues, developing solutions, and standardizing fixes to improve fleet uptime and reliability.
