Semiconductor Jobs

• Bristol
• Hybrid · 4 days in office
• Lead · manages people

Lead a Bristol team of analog IC design engineers, spanning associate to senior level, with direct oversight of performance, development and recruitment. The role is hands-on, guiding complex design work while managing project schedules, budgets and cross-functional priorities for optical communications ICs such as laser drivers, TIAs and transceivers.

SiGe BiCMOS · CMOS · GaAs +2

• Sevenoaks
• Hybrid · 4 days in office
• Lead · manages people

Leads a multidisciplinary team of analog circuit and layout engineers across multiple high-speed IC product lines, owning the full NPI lifecycle from product definition to volume production. Drives tape-out, qualification, post-silicon bring-up and performance optimisation for TIAs and laser driver ICs up to 200G, working with teams in Stansted and Ottawa.

SAP

• Edinburgh
• Hybrid
• Lead
• Permanent

Provide technical leadership for a global engineering compute and design-data-management environment, combining hands-on CAD work with infrastructure ownership. You will own Perforce Helix and IPLM methodologies, build Python and shell automation, and guide migration from legacy data platforms. The role spans Linux compute environments, EDA tool configuration, documentation and training across distributed semiconductor teams.

Perforce Helix · Methodics IPLM · Cadence Virtuoso +4

• Swindon
• Hybrid
• Lead
• Permanent

Provide technical leadership for a global engineering compute and design-data-management environment, combining hands-on CAD work with Perforce Helix and IPLM-based data management. You will develop Linux-based engineering environments, Python and shell automation, project/workspace methodologies, and migration paths from legacy platforms, while supporting EDA tool integration and training engineering teams.

Perforce Helix · Methodics IPLM · Cadence Virtuoso +3

• Whiteley
• £50,000 – £80,000 pa
• Senior

Design and optimise capacitive sensing architectures, develop and verify RTL in Verilog/SystemVerilog, and write embedded C/C++ software for sensing and signal processing. Lead silicon bring-up, debugging and validation across analogue, digital and firmware domains, collaborating with global teams on HMI solutions.

Verilog · SystemVerilog · C/C++ +7

• Edinburgh
• On-site
• Entry level
• Internship

Work alongside experienced engineers on the design, simulation, and characterization of high-performance analog and mixed-signal ICs, including amplifiers, filters, data converters, and clocking solutions. Gain hands-on experience with Cadence and SPICE across circuit design, layout, silicon validation, and laboratory testing throughout the full IC development lifecycle.

Cadence · SPICE · Oscilloscopes +3

• Edinburgh
• Entry level
• Internship

Join a Consumer Audio design team in Edinburgh to work on real mixed-signal IC development, from circuit architecture research and feasibility studies to transistor-level design, simulation and verification of analog blocks. You will build testbenches, analyse trade-offs around noise, distortion and power, and collaborate with layout engineers through physical implementation and design reviews.

Cadence Virtuoso · Spectre · MATLAB +3

• Colchester
• £50,000 – £57,000 pa

Responsible for the electrical design and testing of new x-ray and bond testing products, including panel and industrial system design with circuit breakers, contactors and wiring looms. Works within a Colchester R&D team serving major semiconductor and electronics manufacturers, using CAD tools such as AutoCAD or Inventor and applying electrical safety standards like IEC61010 and NPA79.

AutoCAD · Inventor

• Oldham

Design, simulate and optimise advanced Bipolar devices or MOSFETs using TCAD tools, working closely with process integration and characterisation teams to turn simulation insights into manufacturable, high-performance devices. The role spans process flow definition, electrical and physical data analysis to improve yield, and support from concept through qualification and production, with documentation of design and simulation results.

TCAD

• Bristol

Integrate IP and subsystems into top-level SoC designs, maintaining build and configuration environments while running synthesis, linting, CDC/RDC and timing checks. Work closely with verification and physical design teams on clean interface hand-offs, debug integration issues across hierarchies, and improve automation flows using Python, Tcl, SystemVerilog or VHDL.

SystemVerilog · VHDL · Python +1

• Bristol
• On-site
• Mid-level
• Permanent

Contribute technically to next-generation AI superchips, delivering sign-off-quality layouts in leading-edge process technologies. Work spans floorplanning, synthesis, place and route, CTS, timing analysis, physical verification and flow/tool development in Tcl and Python, collaborating closely with RTL, verification, DFT, architecture and packaging teams. Engineers are trusted to own their designs and improve flows, methodologies and infrastructure.

Tcl · Python · GDSII +7

• London
• Hybrid
• Mid-level

Own the full electronics development lifecycle for photonic computing hardware, from analogue and mixed-signal circuit design through schematic capture, PCB layout, prototyping and lab verification. Work alongside physicists, optical and embedded software engineers in a collaborative R&D team, testing with oscilloscopes and spectrum analysers and supporting integration and EMC.

ADC · DAC · Oscilloscopes +1

• Cambridge
• On-site
• Senior
• Permanent

Design and layout of GaN power ICs using EDA tools, covering schematic capture, analog simulation, chip layout review, PEX and PLS. The role also involves wafer-level and packaged device testing, SPICE model development, and supporting patent and IP management within a growing R&D engineering team.

EDA Tools · SPICE · GaN

• Cambridge
• Mid-level

Executes verification strategies for mixed-signal IP and FlexICs to ensure right-first-time tapeouts, working closely with digital and analog designers. Builds test bench environments, debugs failures, and produces verification reports and coverage statistics across the design flow. Requires strong SystemVerilog and verification methodology knowledge, with UVM highly desirable.

SystemVerilog · UVM · Verilog-AMS +1

• Cambridge
• On-site
• Senior
• Permanent

Design GaN power ICs and Si gate drivers using EDA tools, covering schematic capture, RTL, analog/digital and mixed-signal simulation, synthesis, STA, PNR and AMS verification. Also develops test solutions, analyses wafer-level and packaged device data, documents designs, debugs ICs and generates IP for patent applications within a growing R&D engineering team.

EDA Tools · GaN · Si Gate Drivers