This role involves designing and integrating analog/mixed-signal circuits for advanced semiconductor packaging and heterogeneous integration. Responsibilities include PHY-level interfaces, custom pad circuits, and working with industry partners to develop and commercialize innovative solutions.
Lead a Bristol team of analog IC design engineers, spanning associate to senior level, with direct oversight of performance, development and recruitment. The role is hands-on, guiding complex design work while managing project schedules, budgets and cross-functional priorities for optical communications ICs such as laser drivers, TIAs and transceivers.
Leads a multidisciplinary team of analog circuit and layout engineers across multiple high-speed IC product lines, owning the full NPI lifecycle from product definition to volume production. Drives tape-out, qualification, post-silicon bring-up and performance optimisation for TIAs and laser driver ICs up to 200G, working with teams in Stansted and Ottawa.
Provide technical leadership for a global engineering compute and design-data-management environment, combining hands-on CAD work with infrastructure ownership. You will own Perforce Helix and IPLM methodologies, build Python and shell automation, and guide migration from legacy data platforms. The role spans Linux compute environments, EDA tool configuration, documentation and training across distributed semiconductor teams.
Provide technical leadership for a global engineering compute and design-data-management environment, combining hands-on CAD work with Perforce Helix and IPLM-based data management. You will develop Linux-based engineering environments, Python and shell automation, project/workspace methodologies, and migration paths from legacy platforms, while supporting EDA tool integration and training engineering teams.
Work alongside experienced engineers on the design, simulation, and characterization of high-performance analog and mixed-signal ICs, including amplifiers, filters, data converters, and clocking solutions. Gain hands-on experience with Cadence and SPICE across circuit design, layout, silicon validation, and laboratory testing throughout the full IC development lifecycle.
Join a Consumer Audio design team in Edinburgh to work on real mixed-signal IC development, from circuit architecture research and feasibility studies to transistor-level design, simulation and verification of analog blocks. You will build testbenches, analyse trade-offs around noise, distortion and power, and collaborate with layout engineers through physical implementation and design reviews.
Responsible for the electrical design and testing of new X-ray and bond testing products, including panel and industrial system design with circuit breakers and contactors, plus wiring looms. Works within a Research and Development team serving major semiconductor and electronics manufacturers, using CAD tools such as AutoCAD or Inventor and applying electrical safety standards like IEC61010 and NPA79.
Design, simulate and optimise advanced Bipolar devices or MOSFETs using TCAD tools, working closely with process integration and characterisation teams to turn simulation insights into manufacturable, high-performance devices. The role spans process flow definition, electrical and physical data analysis to improve yield, and support from concept through qualification and production, with documentation of design and simulation results.
Own the full electronics development lifecycle for photonic computing hardware, from analogue and mixed-signal circuit design through schematic capture, PCB layout, prototyping and lab verification. Work alongside physicists, optical and embedded software engineers in a collaborative R&D team, testing with oscilloscopes and spectrum analysers and supporting integration and EMC.
Design and layout of GaN power ICs using EDA tools, covering schematic capture, analog simulation, chip layout review, PEX and PLS. The role also involves wafer-level and packaged device testing, SPICE model development, and supporting patent and IP management within a growing R&D engineering team.
Own end-to-end physical implementation of complex ASIC/SoC designs, from synthesis through floorplanning, CTS, routing and sign-off, with potential full-chip ownership. Work with logic, verification, DFT and process teams to optimise PPA, power integrity and manufacturability on advanced nodes, using Cadence, Synopsys and Calibre flows plus AI-assisted design tools.
Owns end-to-end physical implementation of complex ASIC/SoC designs, covering floorplanning, placement, CTS, routing, STA, power planning and sign-off, with potential full-chip ownership. Works with RTL, verification, DFT and foundry teams on advanced nodes, developing flows in Cadence Innovus, Synopsys Fusion Compiler and Calibre, and applying AI tools to improve design productivity.
Executes verification strategies for mixed-signal IP and FlexICs to ensure right-first-time tapeouts, working closely with digital and analog designers. Builds test bench environments, debugs failures, and produces verification reports and coverage statistics across the design flow. Requires strong SystemVerilog and verification methodology knowledge, with UVM highly desirable.
Design GaN power ICs and Si gate drivers using EDA tools, covering schematic capture, RTL, analog/digital and mixed-signal simulation, synthesis, STA, PNR and AMS verification. Also develops test solutions, analyses wafer-level and packaged device data, documents designs, debugs ICs and generates IP for patent applications within a growing R&D engineering team.
