Semiconductor Jobs

• Edinburgh
• Entry level
• Internship

Join a Consumer Audio design team in Edinburgh to work on real mixed-signal IC development, from circuit architecture research and feasibility studies to transistor-level design, simulation and verification of analog blocks. You will build testbenches, analyse trade-offs around noise, distortion and power, and collaborate with layout engineers through physical implementation and design reviews.

Cadence Virtuoso · Spectre · MATLAB +3

• Edinburgh
• On-site
• Entry level
• Internship

Work alongside experienced engineers on the design, simulation, and characterization of high-performance analog and mixed-signal ICs, including amplifiers, filters, data converters, and clocking solutions. Gain hands-on experience with Cadence and SPICE across circuit design, layout, silicon validation, and laboratory testing throughout the full IC development lifecycle.

Cadence · SPICE · Oscilloscopes +3

• Sevenoaks
• Hybrid · 4 days in office
• Lead · manages people

Leads a multidisciplinary team of analog circuit and layout engineers across multiple high-speed IC product lines, owning the full NPI lifecycle from product definition to volume production. Drives tape-out, qualification, post-silicon bring-up and performance optimisation for TIAs and laser driver ICs up to 200G, working with teams in Stansted and Ottawa.

SAP

• Sevenoaks
• Hybrid · 4 days in office
• Entry level

Designs analogue and mixed-signal subsystems for high-speed TIA and laser driver ICs supporting data rates up to 200G, taking ownership of blocks from concept through validation and volume production. Works with layout, verification and product teams on performance, power and area targets, using Cadence tools within a Stansted and Ottawa design centre.

Cadence · Verilog-AMS · SystemVerilog

• Edinburgh
• Manages people
• Permanent

Owns the full analog and mixed-signal development cycle for IC products, from specification and system architecture through IP requirements, verification planning and layout. Works with product definition, marketing, project management and cross-functional test, product engineering and quality teams, and mentors team members. Requires precision analog, power management and high-voltage BCD design expertise.

• Edinburgh
• Senior
• Permanent

Owns architecture definition, modeling and technical leadership for PMIC and advanced DC/DC converter products from concept through silicon validation. Uses tools such as Simplis and Simulink to analyze stability, transient response and fault behavior, and works across analog, digital, verification and test teams to align architecture intent with implementation.

Simplis · Simulink · Multi-Level Converter (MLC)

• Cambridge
• Mid-level

Executes verification strategies for mixed-signal IP and FlexICs to ensure right-first-time tapeouts, working closely with digital and analog designers. Builds test bench environments, debugs failures, and produces verification reports and coverage statistics across the design flow. Requires strong SystemVerilog and verification methodology knowledge, with UVM highly desirable.

SystemVerilog · UVM · Verilog-AMS +1

• Cambridge
• On-site
• Senior
• Permanent

Design and layout of GaN power ICs using EDA tools, covering schematic capture, analog simulation, chip layout review, PEX and PLS. The role also involves wafer-level and packaged device testing, SPICE model development, and supporting patent and IP management within a growing R&D engineering team.

EDA Tools · SPICE · GaN

• Cork, Ireland
• Hybrid
• £86,324 – £103,589 pa
• Senior
• Permanent

Own verification of mixed-signal ICs from test planning through final sign-off, building and maintaining UVM testbenches, coverage models and regression suites. Work closely with analog and digital design teams to catch issues early, track coverage closure, and help shape the team's verification approach while supporting other engineers.

UVM · SystemVerilog · Verilog-AMS

• Cambridge
• On-site
• Senior
• Permanent

Design GaN power ICs and Si gate drivers using EDA tools, covering schematic capture, RTL, analog/digital and mixed-signal simulation, synthesis, STA, PNR and AMS verification. Also develops test solutions, analyses wafer-level and packaged device data, documents designs, debugs ICs and generates IP for patent applications within a growing R&D engineering team.

EDA Tools · GaN · Si Gate Drivers

• Cork, Ireland
• Hybrid · 3 days in office
• £103,589 – £129,486 pa
• Lead · manages people
• Permanent

Lead and grow a verification team while remaining hands-on with mixed-signal power ICs. You define verification strategy, methodology and sign-off criteria, architect UVM/SystemVerilog environments at block, subsystem and SoC level, and own verification plans, regressions and coverage closure. Works closely with design, firmware, applications and test teams, with three days a week on site in Cork.

Cadence vManager · vPlans · SV-RNM +3

• Didcot
• Hybrid · 4 days in office
• £41,414 – £67,481 pa
• Senior
• Contract

Develop and debug HDL firmware for Xilinx FPGAs in Vivado, implementing full-cycle designs for magnet power supplies on the Diamond-II upgrade, including feedback control, filtering and interlock state machines. Work with ADCs, DACs, memory and microcontrollers, verifying designs via simulation and on-hardware testing, and collaborate with hardware and control engineers on Ethernet-based interfaces.

Xilinx · Vivado · MATLAB +7