Semiconductor Jobs

• Chandler, United States
• £120,000 – £170,000 pa
• Senior

Lead the design, development and debug of complex FPGA SoC systems for satellite communications, covering IP integration, high-performance RTL and firmware. Work spans VHDL/SystemVerilog, Xilinx Vivado and Altera Quartus, AXI/APB SoC debug, timing analysis and gigabit transceiver protocols within a Platforms and FPGA SoC Group.

Xilinx Vivado · Altera Quartus · ModelSim +7

• Oxford
• Hybrid
• £60,000 – £80,000 pa
• Senior

Design, simulate and implement DSP algorithms for telecommunications and sensing, then turn them into FPGA firmware in VHDL and/or Verilog. You'll own simulations, testbenches and verification plans, support hardware integration and space-system qualification, and maintain existing firmware while contributing technical leadership across complex programmes.

Xilinx Versal AI Engines · SoC · Vector Processors

• Chelmsford

Hands-on role spanning clean-room and office work, owning verification and test across space and science imaging detector projects. You define test flows, commission and script EGSE/OGSE/MGSE equipment, run functional, electrical, mechanical and environmental campaigns to ECSS standards, and train operations staff. Works closely with project, product assurance and manufacturing teams.

MATLAB · Python · Microsoft Excel +6

• Chelmsford
• On-site
• Entry level
• Shift work

Assembly and test operator role ensuring timely throughput of imaging devices while meeting quality requirements. Duties include microscope inspection, setting up and running tools, maintaining production records and reporting progress to the line manager, working in a cleanroom on alternating double day shifts.

• Cambridge
• Hybrid
• Mid-level

Design and implement FPGA-based SoC systems for cutting-edge thermal imaging and augmented reality products, contributing reusable modules to a shared library. Work within a multidisciplinary hardware, software and mechanical team, using VHDL, Verilog, SystemVerilog verification, Python and low-power design techniques.

FPGA · VHDL · Verilog +2

• Cambridge
• Hybrid
• Mid-level

Design and implement FPGA-based SoC systems for cutting-edge thermal imaging and augmented reality products, contributing reusable modules to a shared library. Work in a multidisciplinary team of hardware, software and mechanical engineers, using VHDL, Verilog, SystemVerilog and Python, with a focus on low-power design and timing constraints.

FPGA · VHDL · Verilog +2

• Oxford
• Hybrid
• Senior
• Permanent

Owns dense, high-layer-count PCB layout from schematic handoff to fabrication release, covering stackups, HDI structures, controlled-impedance routing, differential pairs and BGA breakout for large FPGAs and custom ASICs. Acts as the main technical contact with fabricators and assembly houses, and sets the footprint libraries, design rules and CAD standards the team works to.

Cadence Allegro · Altium · Gerber +7

• Oxford
• Hybrid
• Senior
• Permanent

Own the embedded software bringing a novel optical AI accelerator to life: Linux kernel and bare-metal device drivers, firmware for control processors, and deterministic RTOS control tasks. Lead board support package bring-up on new custom silicon revisions, debugging with JTAG, scopes and logic analysers, and set the embedded team's coding standards and test methodology.

Linux · JTAG · SWD +3

• Oxford
• Lead · manages people

Lead a three-person electronics team within the Systems group, acting as a player-coach with roughly 60% leadership and 40% hands-on design. Own the electronics roadmap for quantum systems, from schematic capture and PCB layout through board and system-level test, including mixed-signal, high-speed digital and QPU drive architecture, while moving prototypes to rack-ready production.

Altium · Jira · Smartsheet +7

• Oxford
• Hybrid
• Senior

Lead validation and characterisation of analogue and mixed-signal ASICs for trapped-ion quantum processors, from test planning and platform development through first-silicon bring-up, debug and system integration. The role spans room-temperature and cryogenic (around 4 K) measurements on packaged parts, chip-on-board assemblies and bare die, with heavy Python automation and test PCB work.

Python · Git · SPI +7

• Edinburgh
• Entry level
• Internship

Graduate engineering roles spanning electronic engineering and software development, working alongside hardware teams on planning, systems architecture, design, debugging and testing. Projects cover IoT smart buildings, automotive radar, vital signs monitoring and 5G infrastructure, with growing focus on machine learning and AI. Based across Edinburgh, Glasgow, Newbury and London.

IoT · 5G · Automotive Radar

• Lincoln
• On-site
• £42,500 – £52,500 pa
• Mid-level
• Permanent

Design, develop and test FPGA-based systems for real-time RF and signal processing in an electronic warfare context. Work hands-on with RFSoC platforms, high-speed ADC/DAC interfaces, VHDL/SystemVerilog and MATLAB/Simulink, supporting lab integration and test with RF instrumentation. Mostly on-site in Lincoln alongside domain specialists and MOD/RAF customer environments.

RFSoC · Vivado · Quartus +5

• Edinburgh
• Entry level
• Internship

Placement students work alongside engineering teams on real, challenging assignments, contributing to product development across electronics, software and computer science. Interns are paired with experienced mentors and treated as extended interview candidates for future full-time roles, with work spanning IoT, automotive radar, healthcare and 5G systems.

5G · IoT

• Whiteley
• £50,000 – £80,000 pa
• Senior

Design and optimise capacitive sensing architectures, develop and verify RTL in Verilog/SystemVerilog, and write embedded C/C++ software for sensing and signal processing. Lead silicon bring-up, debugging and validation across analogue, digital and firmware domains, collaborating with global teams on HMI solutions.

Verilog · SystemVerilog · C/C++ +7

• Fareham
• £55,000 – £65,000 pa
• Senior

Lead algorithm development for RISC-V-based capacitive touch controllers, owning projects from problem definition and modelling through experimentation, optimisation and validation on real hardware. Work spans sensor physics, mixed-signal electronics and DSP, designing filtering, calibration and noise-rejection algorithms while mentoring junior colleagues.

MATLAB · Python · RISC-V +5