Semiconductor Jobs

Platform Recruitment · Coventry · £40,000 – £60,000 pa

Work across the full FPGA design cycle, from requirements analysis and specification through RTL design, implementation and verification. Define module architectures, run synthesis and timing analysis, and integrate FPGAs into target hardware, using VHDL or Verilog and leading vendor tools alongside senior engineers and system architects.

Renesas Electronics · Edinburgh

Owns verification of complex digital and mixed-signal ASIC designs, building SystemVerilog/UVM testbenches and running block-level to full-chip simulation, coverage and regression. Includes gate-level simulation with SDF timing annotation and mentoring junior engineers. Hybrid role with three set office days in Edinburgh.

Eclectic Recruitment · Stevenage · £70,000 – £85,000 pa

Lead a team of FPGA and digital design engineers while providing hands-on technical direction across FPGA architecture, RTL design, simulation, synthesis, timing closure and hardware validation. Own project execution including planning, estimation, scheduling and risk management, and work with Systems, Software, Hardware and Verification teams to deliver integrated solutions from concept through to production.

Cadence · Edinburgh

Develops verification and emulation environments for complex Chiplet designs, building UVM-SV scoreboards, functional coverage, and SystemVerilog assertions for formal and simulation. Integrates Cadence VIP and accelerated VIP, manages vPlans in vManager, and maintains automated regression environments using Jenkins and GIT within an experienced Chiplet team.

IonQ · Oxford

Architect and maintain UVM/SystemVerilog verification environments for complex FPGA designs, defining verification plans with constrained-random testing and functional coverage. Build automated regression suites and CI pipelines, collaborating with RTL engineers to debug and ensure reliable quantum control systems.

SoCode · Cambridge · £45,000 – £55,000 pa

Own significant blocks of RTL from specification through implementation, verification and into working hardware, focused on physical layer design in the communications space. Work alongside senior and principal engineers on digital RF and fixed-point DSP, with hands-on lab time on AMD/Xilinx FPGA platforms. A new role in a small, established team with low attrition.

Platform Recruitment · Cambridge · £100,000 – £160,000 pa

Design and develop reusable FPGA modules in SystemVerilog for deployment across multiple next-generation products, with RTL verification and timing closure work. You'll write specifications, review code and documentation, and collaborate with hardware, software and mechanical engineers in a hybrid Cambridge team.

Analog Devices · Edinburgh

Implements and verifies digital logic for mixed-signal SoCs used in high-performance power systems, covering RTL development, synthesis, static timing analysis and DFT insertion. Works with analog, firmware and validation teams on integration, silicon bring-up and lab debug, with scope to improve methodology and automation.

Amazon · Cambridge

Architect and implement SoC designs for Blink/Ring smart home cameras and doorbells, owning the flow from RTL delivery through synthesis, power analysis and timing closure. The role also involves defining microarchitecture specs, mentoring junior engineers, and evaluating emerging IP blocks in a vertically integrated environment spanning architectural modelling to post-silicon validation.

Cambridge GaN Devices · Cambridge

Design GaN power ICs and Si gate drivers using EDA tools, covering schematic capture, RTL, analog/digital and mixed-signal simulation, synthesis, STA, PNR and AMS verification. Also develops test solutions, analyses wafer-level and packaged device data, documents designs, debugs ICs and generates IP for patent applications within a growing R&D engineering team.

Hexwired Recruitment Limited · Southampton · £65,000 – £85,000 pa

Verification of RTL implementations to ensure designs meet required standards before deployment, working with SystemVerilog and UVM in a Linux environment. The role sits within an expanding electronics manufacturer and involves scripting in Python, TCL or Bash alongside digital ASIC/FPGA verification work.

Cortech Talent Solutions · Stirling · £40,000 – £65,000 pa

Develop, test and debug embedded software for electronics, supporting integration of microprocessors, microcontrollers, FPGAs and SoC devices. Assist with FPGA development including RTL design, simulation and verification using Verilog and VHDL, and perform system-level testing and hardware/software integration for flight-computer solutions.

Copello · Bristol · £80,000 – £900,000 pa

Take technical ownership of FPGA and programmable logic design for advanced gimbal payload systems, covering video capture and processing, sensor and high-speed serial interfaces, and real-time pointing and stabilisation control. Lead RTL design, verification, synthesis and hardware bring-up, taking in-house boards from prototype to qualified production while mentoring other engineers.

Anonymous · London

Develops FPGA-based digital control hardware for next-generation photonic quantum computing systems, covering architecture, RTL design, simulation, synthesis, timing analysis and verification. Works in a multidisciplinary R&D team with electronics engineers, physicists and software developers on high-speed, low-latency control and signal processing, including ADC/DAC interfacing and hardware bring-up.

The University of Manchester · Manchester · £21,805 pa

A 3.5-year funded PhD designing a Smart Network-on-Chip, an asynchronous communication fabric with intelligence built into its microarchitecture, to manage congestion in 2.5D chiplet systems. The work replaces static routing heuristics with data-driven, learning-based policies, building on an existing RTL-verified asynchronous NoC IP, with possible directions in lightweight inference engines and distributed adaptive traffic management.