Semiconductor Jobs

• Bristol
• On-site
• Mid-level
• Permanent

Contribute technically to next-generation AI superchips, delivering sign-off-quality layouts in leading-edge process technologies. Work spans floorplanning, synthesis, place and route, CTS, timing analysis, physical verification and flow/tool development in Tcl and Python, collaborating closely with RTL, verification, DFT, architecture and packaging teams. Engineers are trusted to own their designs and improve flows, methodologies and infrastructure.

Tcl · Python · GDSII +7

• Edinburgh
• On-site
• Entry level
• Internship

Join a collaborative Edinburgh team developing low-power analog and power-management IP for highly integrated mixed-signal ICs. The intern contributes to architecture, transistor-level design, simulation and verification of DC/DC converter IP such as buck, boost and buck-boost topologies, including analog sub-circuits like error amplifiers, comparators and gate drivers. Work spans behavioural modelling, layout review and potentially laboratory silicon evaluation.

Cadence Virtuoso · Spectre · SIMPLIS +2

• Bristol

Integrate IP and subsystems into top-level SoC designs, maintaining build and configuration environments while running synthesis, linting, CDC/RDC and timing checks. Work closely with verification and physical design teams on clean interface hand-offs, debug integration issues across hierarchies, and improve automation flows using Python, Tcl, SystemVerilog or VHDL.

SystemVerilog · VHDL · Python +1

• Cambridge
• On-site
• £45,000 – £55,000 pa
• Mid-level

Own significant blocks of RTL from specification through implementation, verification and into working hardware, focused on physical layer design in the communications space. Work alongside senior and principal engineers on digital RF and fixed-point DSP, with hands-on lab time on AMD/Xilinx FPGA platforms. A new role in a small, established team with low attrition.

AMD · Xilinx · MATLAB

• Oldham

Design, simulate and optimise advanced Bipolar devices or MOSFETs using TCAD tools, working closely with process integration and characterisation teams to turn simulation insights into manufacturable, high-performance devices. The role spans process flow definition, electrical and physical data analysis to improve yield, and support from concept through qualification and production, with documentation of design and simulation results.

TCAD

• Edinburgh
• On-site
• Entry level
• Internship

Work alongside experienced engineers on the design, simulation, and characterization of high-performance analog and mixed-signal ICs, including amplifiers, filters, data converters, and clocking solutions. Gain hands-on experience with Cadence and SPICE across circuit design, layout, silicon validation, and laboratory testing throughout the full IC development lifecycle.

Cadence · SPICE · Oscilloscopes +3

• Oxford
• Hybrid · 3 days in office
• Senior

Integrate all features needed to operate quantum computers into complex multi-layer chips, guiding designs from requirements through layout and tape-out. Work with scientists and fabrication engineers on ion trapping chips, handling metal-track routing and photonics/CMOS interfaces. Hybrid role, three days per week in the Oxford office.

GDSFactory · Cadence

• Oxford
• Hybrid
• Senior

Architect and maintain UVM/SystemVerilog verification environments for complex FPGA designs, defining verification plans with constrained-random testing and functional coverage. Build automated regression suites and CI pipelines, collaborating with RTL engineers to debug and ensure reliable quantum control systems.

SystemVerilog · UVM · Python

• Oxford
• Hybrid
• Senior · manages people
• Permanent

Owns a Python-based performance and power modelling framework predicting how photonic AI hardware runs real inference workloads, covering compute engines, interconnect, memory and bridge interfaces. Characterises operators against hardware, RTL or emulation, builds compiler-agnostic MLIR interfaces and runs benchmarks to give architecture and compiler teams a shared source of truth.

Python · MLIR · UL Procyon +7

• Bedford
• On-site
• £43,000 – £55,000 pa
• Senior

Take mixed electrical and electronic designs from concept to completion within a structured phase-gate process, covering analogue, digital, microprocessor and FPGA design, power electronics, simulation, test and PCB layout. Work on defence and aerospace hardware for harsh environments, using Altium, JTAG debug and Windchill, with ownership of processes, supplier reviews and compliance documentation.

Altium · Windchill · PLM +1

• Edinburgh
• Senior · manages people
• Permanent

Lead the design and verification of CMOS analog blocks for custom mixed-signal ASICs, taking technical ownership of full-chip or major system-level blocks from specification through to production ramp. The role combines hands-on circuit design with mentoring a team of engineers, working alongside digital, layout, DFT and test teams, and driving silicon debug and characterisation.

Cadence · EDA

• London
• Hybrid
• Mid-level
• Permanent

Develops FPGA-based digital control hardware for next-generation photonic quantum computing systems, covering architecture, RTL design, simulation, synthesis, timing analysis and verification. Works in a multidisciplinary R&D team with electronics engineers, physicists and software developers on high-speed, low-latency control and signal processing, including ADC/DAC interfacing and hardware bring-up.

Xilinx Vivado · Intel Quartus · ADC +2

• Coventry
• On-site
• £21,805 pa
• Entry level
• Contract

Develops medium-voltage solid-state transformer cells for hyperscale AI data centres and net-zero grids, tackling high-frequency power conversion, compact magnetic links and electrical-thermal degradation under high-dv/dt stress. Combines multi-physics finite-element modelling in ANSYS/COMSOL with experimental validation in a high-voltage power electronics lab, culminating in a scaled hardware prototype.

ANSYS · COMSOL · FPGA +1

• Durham
• On-site
• Lead · manages people

Owns metal-oxide PVD process development, qualification and sustaining on 300mm production tools, defining process windows and driving SPC, Cpk and root-cause investigations for yield-limiting film issues. Combines deep technical leadership of reactive sputtering with line management of a small deposition team, partnering with equipment, integration and reliability engineers.

R · R-Markdown · JMP +1