Semiconductor Jobs

• Guildford
• On-site
• £40,000 – £46,000 pa
• Entry level

Join a multidisciplinary team building integrated software-hardware systems for defence and security, spanning low-power embedded devices to high-throughput server applications. You'll apply C/C++, FPGA, and electronics skills to complex projects combining custom hardware with innovative software, with labs and prototyping facilities on site.

FPGA · VHDL · PCB

• Oldham

Design, simulate and optimise advanced Bipolar devices or MOSFETs using TCAD tools, working closely with process integration and characterisation teams to turn simulation insights into manufacturable, high-performance devices. The role spans process flow definition, electrical and physical data analysis to improve yield, and support from concept through qualification and production, with documentation of design and simulation results.

TCAD

• Newbury
• On-site
• Entry level
• Internship

Join the CSS design verification team to validate IP and subsystem-level designs for high-performance semiconductor products. You will develop System Verilog/UVM testbenches, run simulations, debug failures, and track functional and assertion coverage alongside design and architecture engineers.

SystemVerilog · Verilog · UVM +7

• Edinburgh
• Entry level
• Internship

Hands-on internship in a design verification team, validating IP and subsystem-level designs for high-performance semiconductor products. You will develop System Verilog/UVM testbenches, run simulations, debug failures, create directed and constrained-random tests, and track functional, code and assertion coverage while supporting regression automation with scripting.

SystemVerilog · Verilog · UVM +7

• United Kingdom
• £50,000 – £70,000 pa
• Senior

Join a Surrey technical consultancy building custom hardware and software solutions for UK government clients, spanning embedded C/C++, FPGAs, PCB design and signal processing. You will mentor junior engineers, drive new project direction and manage client relationships through reports and presentations. Requires UK nationality due to project sensitivity.

FPGA · VHDL · PCB

• Cheltenham
• £45,000 – £55,000 pa
• Entry level

Contribute to advanced electronic systems by implementing signal, image and data-processing algorithms in VHDL, designing PCBs with FPGAs, SoCs and high-speed interfaces, and completing schematic capture in OrCAD. The role also covers test firmware, embedded software, Linux device drivers and bringing up newly designed boards within a multidisciplinary engineering team.

FPGA · VHDL · OrCAD +4

• London
• Hybrid
• Mid-level
• Permanent

Develops FPGA-based digital control hardware for next-generation photonic quantum computing systems, covering architecture, RTL design, simulation, synthesis, timing analysis and verification. Works in a multidisciplinary R&D team with electronics engineers, physicists and software developers on high-speed, low-latency control and signal processing, including ADC/DAC interfacing and hardware bring-up.

Xilinx Vivado · Intel Quartus · ADC +2

• Cambridge

Hands-on development of kernel generation and computational graph optimizations for next-generation NVIDIA GPUs, solving complex compilation problems for AI inference and training workloads. The role involves co-designing future silicon with software, hardware and research teams, and optimizing datacenter-scale AI deployments using MLIR, C/C++ and Python.

MLIR · GPU · CPU +1

• Coventry
• On-site
• £21,805 pa
• Entry level
• Contract

Develops medium-voltage solid-state transformer cells for hyperscale AI data centres and net-zero grids, tackling high-frequency power conversion, compact magnetic links and electrical-thermal degradation under high-dv/dt stress. Combines multi-physics finite-element modelling in ANSYS/COMSOL with experimental validation in a high-voltage power electronics lab, culminating in a scaled hardware prototype.

ANSYS · COMSOL · FPGA +1

• Manchester
• £21,805 pa
• Entry level
• Contract

A 3.5-year funded PhD designing a Smart Network-on-Chip, an asynchronous communication fabric with intelligence built into its microarchitecture, to manage congestion in 2.5D chiplet systems. The work replaces static routing heuristics with data-driven, learning-based policies, building on an existing RTL-verified asynchronous NoC IP, with possible directions in lightweight inference engines and distributed adaptive traffic management.

CPUs · GPUs · AI Accelerators +5

• Durham
• On-site
• Lead · manages people

Owns metal-oxide PVD process development, qualification and sustaining on 300mm production tools, defining process windows and driving SPC, Cpk and root-cause investigations for yield-limiting film issues. Combines deep technical leadership of reactive sputtering with line management of a small deposition team, partnering with equipment, integration and reliability engineers.

R · R-Markdown · JMP +1

• Bristol
• Hybrid
• Mid-level
• Permanent

Contribute to fundamental and applied AI research, generating ideas, designing experiments and translating them into scalable implementations using PyTorch or JAX. The role emphasises lower-level programming (C++/CUDA/Triton) and hardware-aware optimisation, with work spanning efficient training and inference, world models, reinforcement learning and life sciences, and results published at NeurIPS, ICML and ICLR.

PyTorch · JAX · XLA +1

• London
• Hybrid
• Mid-level
• Permanent

Contribute to fundamental and applied AI research, generating ideas, designing experiments and translating them into scalable implementations. Work spans efficient training and inference, world models, reinforcement learning and life sciences, with a focus on hardware-aware algorithms and low-level performance optimisation in C++/CUDA/Triton. Collaborate with silicon and software engineers and publish at NeurIPS, ICML and ICLR.

PyTorch · JAX · CUDA +3

• Didcot
• Hybrid · 4 days in office
• £41,414 – £67,481 pa
• Senior
• Contract

Develop and debug HDL firmware for Xilinx FPGAs in Vivado, implementing full-cycle designs for magnet power supplies on the Diamond-II upgrade, including feedback control, filtering and interlock state machines. Work with ADCs, DACs, memory and microcontrollers, verifying designs via simulation and on-hardware testing, and collaborate with hardware and control engineers on Ethernet-based interfaces.

Xilinx · Vivado · MATLAB +7

• Bristol
• Hybrid · 4 days in office
• Senior

Architect test strategies for high-speed mixed-signal and RF SiGe products, from first silicon to mass production, covering 200Gbps+ SerDes, CDRs and signal conditioning. Sets DFT and testability standards, builds reusable test IP, and leads NPI transfers to high-volume OSATs while mentoring engineers.

Advantest V93000 · SmarTest 7/8 · C/C++ +7