Semiconductor Jobs

• Whiteley
• £50,000 – £80,000 pa
• Senior

Design and optimise capacitive sensing architectures, develop and verify RTL in Verilog/SystemVerilog, and write embedded C/C++ software for sensing and signal processing. Lead silicon bring-up, debugging and validation across analogue, digital and firmware domains, collaborating with global teams on HMI solutions.

Verilog · SystemVerilog · C/C++ +7

• Sevenoaks
• Hybrid · 4 days in office
• Entry level

Designs analogue and mixed-signal subsystems for high-speed TIA and laser driver ICs supporting data rates up to 200G, taking ownership of blocks from concept through validation and volume production. Works with layout, verification and product teams on performance, power and area targets, using Cadence tools within a Stansted and Ottawa design centre.

Cadence · Verilog-AMS · SystemVerilog

• Cambridge
• On-site
• Senior
• Permanent

Design and layout of GaN power ICs using EDA tools, covering schematic capture, analog simulation, chip layout review, PEX and PLS. The role also involves wafer-level and packaged device testing, SPICE model development, and supporting patent and IP management within a growing R&D engineering team.

EDA Tools · SPICE · GaN

• Sevenoaks
• Lead

Leads the design and development of high-speed analog ICs from concept through to volume production, acting as technical authority on circuit architecture and chip subsystems. Works across Stansted and Ottawa design centres on transimpedance amplifiers and laser drivers for datacentres, 5G and fibre-to-the-home, mentoring junior engineers and collaborating with cross-functional teams.

Cadence · Verilog-AMS · SystemVerilog +6

• Cambridge
• On-site
• Senior
• Permanent

Design GaN power ICs and Si gate drivers using EDA tools, covering schematic capture, RTL, analog/digital and mixed-signal simulation, synthesis, STA, PNR and AMS verification. Also develops test solutions, analyses wafer-level and packaged device data, documents designs, debugs ICs and generates IP for patent applications within a growing R&D engineering team.

EDA Tools · GaN · Si Gate Drivers

• Edinburgh
• Entry level
• Internship

Join a Consumer Audio design team in Edinburgh to work on real mixed-signal IC development, from circuit architecture research and feasibility studies to transistor-level design, simulation and verification of analog blocks. You will build testbenches, analyse trade-offs around noise, distortion and power, and collaborate with layout engineers through physical implementation and design reviews.

Cadence Virtuoso · Spectre · MATLAB +3

• Edinburgh
• On-site
• Entry level
• Internship

Join a collaborative Edinburgh team developing low-power analog and power-management IP for highly integrated mixed-signal ICs. The intern contributes to architecture, transistor-level design, simulation and verification of DC/DC converter IP such as buck, boost and buck-boost topologies, including analog sub-circuits like error amplifiers, comparators and gate drivers. Work spans behavioural modelling, layout review and potentially laboratory silicon evaluation.

Cadence Virtuoso · Spectre · SIMPLIS +2

• Oxford
• Hybrid · 3 days in office
• Senior

Integrate all features needed to operate quantum computers into complex multi-layer chips, guiding designs from requirements through layout and tape-out. Work with scientists and fabrication engineers on ion trapping chips, handling metal-track routing and photonics/CMOS interfaces. Hybrid role, three days per week in the Oxford office.

GDSFactory · Cadence

• Fareham
• £55,000 – £65,000 pa
• Senior

Lead algorithm development for RISC-V-based capacitive touch controllers, owning projects from problem definition and modelling through experimentation, optimisation and validation on real hardware. Work spans sensor physics, mixed-signal electronics and DSP, designing filtering, calibration and noise-rejection algorithms while mentoring junior colleagues.

MATLAB · Python · RISC-V +5

• Cambridge
• On-site
• Mid-level
• Permanent

Designs and develops RF front-end circuits and functional blocks, integrating them into low-loss, high-performance multi-chip modules. Works closely with IC designers, systems, algorithm and software teams to optimise module performance and define test plans in a fast-moving fabless semiconductor start-up.

• Darlington

Characterise and model compound semiconductor devices, developing compact models for GaN and GaAs technologies and running DC, pulsed I-V, noise and small/large-signal RF testing. You will build and validate MMIC Process Design Kits, support customer design queries and work with design engineers on new process development. Requires UK nationality and security clearance.

IC-CAP · ADS · Microwave Office +2

• Edinburgh
• Manages people
• Permanent

Owns the full analog and mixed-signal development cycle for IC products, from specification and system architecture through IP requirements, verification planning and layout. Works with product definition, marketing, project management and cross-functional test, product engineering and quality teams, and mentors team members. Requires precision analog, power management and high-voltage BCD design expertise.

• Newton Aycliffe
• Mid-level

Generates, verifies and releases MMIC integrated circuit layouts and mask reticle designs, taking them from initial concept through to mask release. Works in a Design Services team, producing mask order documentation and reticle records while liaising with engineers, programme managers, customers and external mask manufacturers.

KLayout · L-Edit · Nazca Design +2

• Newcastle upon Tyne
• Lead

Develops and maintains a C++ codebase for next-generation EDA tools, focusing on computational geometry, geometry manipulation and algorithmic complexity for sub-20nm IC design. Involves writing design, function and test specifications, interfacing with build and regression systems, and collaborating with a global cross-functional team.

Qt · Linux · Unix

• Cambridge
• Lead · manages people

Technical leadership role owning product-level characterisation strategy, translating requirements and risks into proportionate test coverage, analysis and reporting. Leads a small team developing automated volume test solutions while hands-on with wafer-level ATE characterisation, RF/analogue test design and large-dataset analysis, presenting findings to stakeholders from project inception through production transfer.

Python · LabVIEW · C# +2