Semiconductor Jobs

• Edinburgh
• Hybrid
• Lead
• Permanent

Provide technical leadership for a global engineering compute and design-data-management environment, combining hands-on CAD work with infrastructure ownership. You will own Perforce Helix and IPLM methodologies, build Python and shell automation, and guide migration from legacy data platforms. The role spans Linux compute environments, EDA tool configuration, documentation and training across distributed semiconductor teams.

Perforce Helix · Methodics IPLM · Cadence Virtuoso +4

• Swindon
• Hybrid
• Lead
• Permanent

Provide technical leadership for a global engineering compute and design-data-management environment, combining hands-on CAD work with Perforce Helix and IPLM-based data management. You will develop Linux-based engineering environments, Python and shell automation, project/workspace methodologies, and migration paths from legacy platforms, while supporting EDA tool integration and training engineering teams.

Perforce Helix · Methodics IPLM · Cadence Virtuoso +3

• Bristol
• £45,000 pa
• Entry level
• Permanent

Join one of four specialist silicon teams — logical design, verification, physical design or design for test — contributing to real AI chip development. You'll work on RTL design, SOC integration, verification methods or physical implementation using industry-standard EDA tools, taking ownership of clear tasks with support from experienced engineers over a two-year programme.

EDA Tools

• Newcastle upon Tyne
• Lead

Develops and maintains a C++ codebase for next-generation EDA tools, focusing on computational geometry, geometry manipulation and algorithmic complexity for sub-20nm IC design. Involves writing design, function and test specifications, interfacing with build and regression systems, and collaborating with a global cross-functional team.

Qt · Linux · Unix

• Newbury
• On-site
• Entry level
• Internship

Join the CSS design verification team to validate IP and subsystem-level designs for high-performance semiconductor products. You will develop System Verilog/UVM testbenches, run simulations, debug failures, and track functional and assertion coverage alongside design and architecture engineers.

SystemVerilog · Verilog · UVM +7

• Edinburgh
• Entry level
• Internship

Hands-on internship in a design verification team, validating IP and subsystem-level designs for high-performance semiconductor products. You will develop System Verilog/UVM testbenches, run simulations, debug failures, create directed and constrained-random tests, and track functional, code and assertion coverage while supporting regression automation with scripting.

SystemVerilog · Verilog · UVM +7

• Cambridge
• On-site
• Senior
• Permanent

Design and layout of GaN power ICs using EDA tools, covering schematic capture, analog simulation, chip layout review, PEX and PLS. The role also involves wafer-level and packaged device testing, SPICE model development, and supporting patent and IP management within a growing R&D engineering team.

EDA Tools · SPICE · GaN

• Bristol
• On-site
• Mid-level
• Permanent

Contribute technically to next-generation AI superchips, delivering sign-off-quality layouts in leading-edge process technologies. Work spans floorplanning, synthesis, place and route, CTS, timing analysis, physical verification and flow/tool development in Tcl and Python, collaborating closely with RTL, verification, DFT, architecture and packaging teams. Engineers are trusted to own their designs and improve flows, methodologies and infrastructure.

Tcl · Python · GDSII +7

• Edinburgh
• Lead

Develops verification and emulation environments for complex Chiplet designs, building UVM-SV scoreboards, functional coverage, and SystemVerilog assertions for formal and simulation. Integrates Cadence VIP and accelerated VIP, manages vPlans in vManager, and maintains automated regression environments using Jenkins and GIT within an experienced Chiplet team.

Cadence Palladium · Cadence VIP · Cadence vManager +3

• Cambridge
• On-site
• Senior
• Permanent

Design GaN power ICs and Si gate drivers using EDA tools, covering schematic capture, RTL, analog/digital and mixed-signal simulation, synthesis, STA, PNR and AMS verification. Also develops test solutions, analyses wafer-level and packaged device data, documents designs, debugs ICs and generates IP for patent applications within a growing R&D engineering team.

EDA Tools · GaN · Si Gate Drivers

• Swindon
• Hybrid
• Senior
• Permanent

Provides technical leadership for a global EDA/CAD compute and engineering infrastructure, spanning Linux environments, LSF batch compute, EDA license servers, Perforce and project/workspace provisioning. Combines hands-on Python and shell automation with architecture, monitoring and capacity planning, working across engineering, CAD and IT/IS teams to keep semiconductor development environments consistent and reliable worldwide.

LSF · Perforce Helix · IPLM +6

• Edinburgh
• On-site
• Entry level
• Internship

Work alongside experienced engineers on the design, simulation, and characterization of high-performance analog and mixed-signal ICs, including amplifiers, filters, data converters, and clocking solutions. Gain hands-on experience with Cadence and SPICE across circuit design, layout, silicon validation, and laboratory testing throughout the full IC development lifecycle.

Cadence · SPICE · Oscilloscopes +3

• Edinburgh
• Senior · manages people
• Permanent

Lead the design and verification of CMOS analog blocks for custom mixed-signal ASICs, taking technical ownership of full-chip or major system-level blocks from specification through to production ramp. The role combines hands-on circuit design with mentoring a team of engineers, working alongside digital, layout, DFT and test teams, and driving silicon debug and characterisation.

Cadence · EDA

• Bristol
• £2,500 pm
• Entry level
• Internship

Join one of four specialist silicon teams—logical design, verification, physical design or design for test—contributing to real AI chip development over a 12-week summer placement. You'll work with industry-standard EDA tools on tasks such as RTL design, SOC integration, verification methods or physical implementation, with support from experienced engineers.

EDA Tools