Semiconductor Jobs

• Bristol
• Hybrid
• Mid-level
• Permanent

Contribute to fundamental and applied AI research, generating ideas, designing experiments and translating them into scalable implementations using PyTorch or JAX. The role emphasises lower-level programming (C++/CUDA/Triton) and hardware-aware optimisation, with work spanning efficient training and inference, world models, reinforcement learning and life sciences, and results published at NeurIPS, ICML and ICLR.

PyTorch · JAX · XLA +1

• London
• Hybrid
• Mid-level
• Permanent

Contribute to fundamental and applied AI research, generating ideas, designing experiments and translating them into scalable implementations. Work spans efficient training and inference, world models, reinforcement learning and life sciences, with a focus on hardware-aware algorithms and low-level performance optimisation in C++/CUDA/Triton. Collaborate with silicon and software engineers and publish at NeurIPS, ICML and ICLR.

PyTorch · JAX · CUDA +3

• Oxford
• Hybrid
• Senior · manages people
• Permanent

Owns a Python-based performance and power modelling framework predicting how photonic AI hardware runs real inference workloads, covering compute engines, interconnect, memory and bridge interfaces. Characterises operators against hardware, RTL or emulation, builds compiler-agnostic MLIR interfaces and runs benchmarks to give architecture and compiler teams a shared source of truth.

Python · MLIR · UL Procyon +7

• Cambridge

Hands-on development of kernel generation and computational graph optimizations for next-generation NVIDIA GPUs, solving complex compilation problems for AI inference and training workloads. The role involves co-designing future silicon with software, hardware and research teams, and optimizing datacenter-scale AI deployments using MLIR, C/C++ and Python.

MLIR · GPU · CPU +1

• Southampton
• £37,369 – £39,560 pa
• Entry level
• Contract

Investigates 2D semiconductors and ferroelectric materials to build non-volatile memory that co-locates storage and processing for low-power AI hardware. Combines materials characterisation, interface engineering and device fabrication at the Southampton Nanofabrication Centre, with short research visits to Cambridge and NPL. Based in the 2D-MINDs team and the ECS Centre for Neuromorphic Technologies.

Raman Spectroscopy · Photoluminescence · AFM +2

• Edinburgh
• Entry level
• Internship

Join a Consumer Audio design team in Edinburgh to work on real mixed-signal IC development, from circuit architecture research and feasibility studies to transistor-level design, simulation and verification of analog blocks. You will build testbenches, analyse trade-offs around noise, distortion and power, and collaborate with layout engineers through physical implementation and design reviews.

Cadence Virtuoso · Spectre · MATLAB +3

• Edinburgh
• On-site
• Entry level
• Internship

Join a collaborative Edinburgh team developing low-power analog and power-management IP for highly integrated mixed-signal ICs. The intern contributes to architecture, transistor-level design, simulation and verification of DC/DC converter IP such as buck, boost and buck-boost topologies, including analog sub-circuits like error amplifiers, comparators and gate drivers. Work spans behavioural modelling, layout review and potentially laboratory silicon evaluation.

Cadence Virtuoso · Spectre · SIMPLIS +2

• Oxford
• Hybrid
• Senior
• Permanent

Owns dense, high-layer-count PCB layout from schematic handoff to fabrication release, covering stackups, HDI structures, controlled-impedance routing, differential pairs and BGA breakout for large FPGAs and custom ASICs. Acts as the main technical contact with fabricators and assembly houses, and sets the footprint libraries, design rules and CAD standards the team works to.

Cadence Allegro · Altium · Gerber +7

• Coventry
• On-site
• £21,805 pa
• Entry level
• Contract

Develops medium-voltage solid-state transformer cells for hyperscale AI data centres and net-zero grids, tackling high-frequency power conversion, compact magnetic links and electrical-thermal degradation under high-dv/dt stress. Combines multi-physics finite-element modelling in ANSYS/COMSOL with experimental validation in a high-voltage power electronics lab, culminating in a scaled hardware prototype.

ANSYS · COMSOL · FPGA +1

• Manchester
• £21,805 pa
• Entry level
• Contract

A 3.5-year funded PhD designing a Smart Network-on-Chip, an asynchronous communication fabric with intelligence built into its microarchitecture, to manage congestion in 2.5D chiplet systems. The work replaces static routing heuristics with data-driven, learning-based policies, building on an existing RTL-verified asynchronous NoC IP, with possible directions in lightweight inference engines and distributed adaptive traffic management.

CPUs · GPUs · AI Accelerators +5

• Bristol
• Remote
• Lead

Customer-facing technical strategist driving design wins for high-speed analog ICs (drivers, TIAs, copper redrivers) with Tier 1 hyperscalers and EMEA optical accounts. Leads co-development of 1.6T/3.2T interconnect, signal integrity and transceiver validation, while also supporting PON and Mobile Transport accounts and influencing product roadmaps.

IEEE 802.3 · OIF · ITU-T PON +7

• Stevenage
• Hybrid
• £65 ph
• Senior
• Contract

Design, simulate and implement DSP algorithms for advanced communications and sensing systems, and develop, test and verify FPGA firmware in VHDL and/or Verilog. Working from system requirements and functional specifications, you support hardware integration and debugging within a multidisciplinary engineering team.

Xilinx Versal AI Engines · LTE

• Oxford
• Hybrid
• £60,000 – £80,000 pa
• Senior

Design, simulate and implement DSP algorithms for telecommunications and sensing, then turn them into FPGA firmware in VHDL and/or Verilog. You'll own simulations, testbenches and verification plans, support hardware integration and space-system qualification, and maintain existing firmware while contributing technical leadership across complex programmes.

Xilinx Versal AI Engines · SoC · Vector Processors

• Germany
• On-site
• Lead
• Permanent

Design, verify and deliver VHDL/Verilog FPGA solutions for complex integrated systems, working with systems, hardware and software teams on real-time, embedded aerospace and defence-grade projects. Duties include timing and area constraints, place-and-route, configuration management, documentation and hardware/system-level integration and verification.

Quartus Prime Pro · ModelSim · Vivado +4

• Sevenoaks
• Hybrid · 4 days in office
• CA$95,000 – CA$122,000 pa
• Senior

Owns new product introduction for high-speed analog and mixed-signal ICs, from concept through volume manufacturing and end-of-life. Defines DfT/DfM requirements, drives ATE test program development, PVT characterisation, ATE-to-bench correlation, yield analysis and DOE-based optimisation. Works cross-functionally with design, test, quality and operations, and mentors junior engineers.

Excel · JMP · Galaxy +6