Senior/Principal Physical Design Engineer
This role involves end-to-end physical implementation of advanced ASIC/SoC designs for AI accelerators, including floorplanning, placement, clock tree synthesis, routing, and sign-off. The engineer will optimise for performance, power, and area (PPA) using industry-standard EDA tools and collaborate closely with RTL, architecture, and process technology teams. Focus areas include timing closure, low-power design, and manufacturability for cutting-edge nodes like 7nm and below.