107 jobs for “verification engineer”
Platform Recruitment Cambridge £100,000 – £160,000 pa
Design and develop reusable FPGA modules in SystemVerilog for deployment across multiple next-generation products, with RTL verification and timing closure work. You'll write specifications, review code and documentation, and collaborate with hardware, software and mechanical engineers in a hybrid Cambridge team.
Sagentia Cambridge
Lead the architecture, design and integration of complex electronic and electromechanical systems from concept through verification, regulatory approval and transfer to manufacture. Manage multiple concurrent development projects, coordinate multidisciplinary teams, and act as the client-facing technical lead, mentoring engineers across electronics and systems disciplines.
Redline Group Devizes £80,000 – £90,000 pa
Translate probabilistic algorithms from Python, C++, MATLAB and pseudocode into pipelined, resource-efficient FPGA RTL, writing custom VHDL from scratch where vendor IP is unsuitable. Architect high-speed data acquisition pipelines using ultra-fast ADCs, PCIe, Ethernet and transceivers, and handle verification, bring-up and timing/power optimisation across multiple clock domains alongside hardware, software, research and ASIC teams.
Huber+Suhner Polatis Cambridge
Design, verify and validate FPGA solutions for optical networking products, implementing VHDL logic on Xilinx Artix-7 devices using Vivado. Work spans requirements capture, test benches, timing closure, CDC analysis and lab bring-up with logic analysers, collaborating closely with electronics and software engineers.
Platform Recruitment Stevenage £65 ph
Design and implement DSP algorithms for advanced communications and sensing systems, developing FPGA firmware using VHDL/Verilog. Work closely with multidisciplinary teams to translate system requirements into firmware solutions and support hardware integration and debugging. Focus on simulation, verification, and formal configuration control throughout the development lifecycle.
Graphcore Bristol £45,000 pa
Graduate role developing firmware for next-generation AI hardware, covering bootup, power control, telemetry and monitoring. You'll write and review code, work with continuous integration and build systems, and collaborate with silicon and hardware teams in Agile ceremonies. Part of a two-year graduate programme with hands-on embedded software development.
Cadence Newcastle upon Tyne
Develops and maintains a C++ codebase for next-generation EDA tools, focusing on computational geometry, geometry manipulation and algorithmic complexity for sub-20nm IC design. Involves writing design, function and test specifications, interfacing with build and regression systems, and collaborating with a global cross-functional team.
Renesas Electronics Edinburgh
Lead the design and verification of CMOS analog blocks for custom mixed-signal ASICs, taking technical ownership of full-chip or major system-level blocks from specification through to production ramp. The role combines hands-on circuit design with mentoring a team of engineers, working alongside digital, layout, DFT and test teams, and driving silicon debug and characterisation.
Analog Devices Edinburgh
Join a Consumer Audio design team in Edinburgh to work on real mixed-signal IC development, from circuit architecture research and feasibility studies to transistor-level design, simulation and verification of analog blocks. You will build testbenches, analyse trade-offs around noise, distortion and power, and collaborate with layout engineers through physical implementation and design reviews.
Analog Devices Edinburgh
Join a collaborative Edinburgh team developing low-power analog and power-management IP for highly integrated mixed-signal ICs. The intern contributes to architecture, transistor-level design, simulation and verification of DC/DC converter IP such as buck, boost and buck-boost topologies, including analog sub-circuits like error amplifiers, comparators and gate drivers. Work spans behavioural modelling, layout review and potentially laboratory silicon evaluation.
IonQ Oxford
Lead validation and characterisation of analogue and mixed-signal ASICs for trapped-ion quantum processors, from test planning and platform development through first-silicon bring-up, debug and system integration. The role spans room-temperature and cryogenic (around 4 K) measurements on packaged parts, chip-on-board assemblies and bare die, with heavy Python automation and test PCB work.
Cambridge GaN Devices Cambridge
Define and architect test hardware for GaN power devices and ICs, covering fixtures, sockets, probing, switching and multi-site parallel setups for static, dynamic and mixed-signal measurements. Lead test hardware workstreams from concept to release, write specifications, review designs, and mentor engineers while shaping the test equipment roadmap.
Graphcore Bristol £45,000 pa
Join the Silicon Architecture team to specify, model and evaluate complex SoC subsystems for next-generation AI hardware, with guidance from experienced architects. Work spans architectural modelling, IP assessment, design trade-offs and silicon bring-up, collaborating across design, verification, hardware and software teams. A two-year graduate programme with mentoring and growing ownership.
Lumai Oxford
Owns a Python-based performance and power modelling framework predicting how photonic AI hardware runs real inference workloads, covering compute engines, interconnect, memory and bridge interfaces. Characterises operators against hardware, RTL or emulation, builds compiler-agnostic MLIR interfaces and runs benchmarks to give architecture and compiler teams a shared source of truth.
Semtech Sevenoaks CA$95,000 – CA$122,000 pa
Owns new product introduction for high-speed analog and mixed-signal ICs, from concept through volume manufacturing and end-of-life. Defines DfT/DfM requirements, drives ATE test program development, PVT characterisation, ATE-to-bench correlation, yield analysis and DOE-based optimisation. Works cross-functionally with design, test, quality and operations, and mentors junior engineers.
