Semiconductor Jobs

• Edinburgh
• Hybrid · 3 days in office
• Senior
• Permanent

Owns verification of complex digital and mixed-signal ASIC designs, building SystemVerilog/UVM testbenches and running block-level to full-chip simulation, coverage and regression. Includes gate-level simulation with SDF timing annotation and mentoring junior engineers. Hybrid role with three set office days in Edinburgh.

Synopsys VCS · Cadence Xcelium · Tcl +4

• Bourne End
• Senior
• Permanent

Serve as technical lead for analog and power solutions, supporting UK and Ireland customers from pre-design through production. Drive design-ins and design-wins via architecture development, schematic and layout reviews, bench validation, and hands-on debug across PMICs, DC/DC, GaN, and signal chain. Act as the field voice back to product divisions while working within the sales team.

PMICs · DC/DC · GaN +7

• Lincoln
• On-site
• £52,000 – £62,000 pa
• Senior
• Permanent

Lead FPGA design, implementation and verification for RF signal processing and high-throughput systems, working on AMD/Xilinx RFSoC and Intel platforms with VHDL, SystemVerilog and MATLAB/Simulink workflows. The role sits within an Electronic Warfare operations group, supporting lab-based integration and test with RF instrumentation while mentoring junior engineers and shaping requirements with stakeholders.

AMD · Xilinx RFSoC · Zynq UltraScale+ +5

• Bristol
• £45,000 pa
• Entry level
• Permanent

Two-year graduate programme spanning Hardware Design and Signal Integrity on the electronic systems behind AI compute platforms. You'll develop circuits, schematics and PCB layouts, or analyse PCIe, Ethernet and DDR interfaces using simulation tools like Mentor Expedition, Ansys HFSS and Keysight ADS, comparing models with lab measurements.

Mentor Expedition · Ansys HFSS · Keysight ADS +3

• Farnborough

Design, develop and test embedded software and firmware for specialist engineering applications, contributing across the full lifecycle from research and prototyping to validation and product development. Work within a multidisciplinary team spanning software, FPGA and hardware engineering, with opportunities to broaden expertise across FPGA, DSP, electronics and RF technologies.

Vivado · Vitis · ModelSim +3

• Bristol
• Hybrid · 4 days in office
• Senior

Lead bench PVT characterization for high-speed optical and electrical signal integrity products, developing automated test environments and analyzing complex datasets. Work with an international team across the UK, Canada, US and Mexico, using Python automation and mentoring junior engineers in a lab-based NPI role.

Python

• Newton Aycliffe
• Mid-level

Integrate individual semiconductor processes into stable, repeatable manufacturing flows that support high yield and product quality. Work with Process, Device, Design, Quality and Production teams across the product lifecycle, from development and qualification to production ramp-up, using SPC, DOE and FMEA in a cleanroom environment.

GaAs · GaN

• Edinburgh
• Entry level
• Internship

Placement students work alongside engineering teams on real, challenging assignments, contributing to product development across electronics, software and computer science. Interns are paired with experienced mentors and treated as extended interview candidates for future full-time roles, with work spanning IoT, automotive radar, healthcare and 5G systems.

5G · IoT

• Durham
• Senior

Lead the development, qualification and transfer of back-end semiconductor assembly processes into high-volume manufacturing, with particular focus on laser processing, die singulation, wafer-on-frame debonding and advanced packaging. Design and execute DOEs, set process windows and control plans, and mentor engineers while supporting new product introductions and customer-driven transfers.

JMP · Minitab · Excel

• Cambridge
• Lead · manages people

Technical leadership role owning product-level characterisation strategy, translating requirements and risks into proportionate test coverage, analysis and reporting. Leads a small team developing automated volume test solutions while hands-on with wafer-level ATE characterisation, RF/analogue test design and large-dataset analysis, presenting findings to stakeholders from project inception through production transfer.

Python · LabVIEW · C# +2

• Bristol
• Lead

Lead advanced manufacturing test strategy for complex circuit board assemblies, defining methods and evaluation criteria across optical and X-ray inspection, in-circuit test, boundary scan and functional test. Set direction, mentor engineers and work closely with design, manufacturing, silicon and CEM partners to improve defect coverage and diagnostic resolution.

JTAG 1149.x · iJTAG · MDA +1

• Sevenoaks
• Lead

Leads the design and development of high-speed analog ICs from concept through to volume production, acting as technical authority on circuit architecture and chip subsystems. Works across Stansted and Ottawa design centres on transimpedance amplifiers and laser drivers for datacentres, 5G and fibre-to-the-home, mentoring junior engineers and collaborating with cross-functional teams.

Cadence · Verilog-AMS · SystemVerilog +6

• Edinburgh
• On-site
• Entry level
• Internship

Join a collaborative Edinburgh team developing low-power analog and power-management IP for highly integrated mixed-signal ICs. The intern contributes to architecture, transistor-level design, simulation and verification of DC/DC converter IP such as buck, boost and buck-boost topologies, including analog sub-circuits like error amplifiers, comparators and gate drivers. Work spans behavioural modelling, layout review and potentially laboratory silicon evaluation.

Cadence Virtuoso · Spectre · SIMPLIS +2

• Oxford
• Hybrid
• Senior

Lead validation and characterisation of analogue and mixed-signal ASICs for trapped-ion quantum processors, from test planning and platform development through first-silicon bring-up, debug and system integration. The role spans room-temperature and cryogenic (around 4 K) measurements on packaged parts, chip-on-board assemblies and bare die, with heavy Python automation and test PCB work.

Python · Git · SPI +7

• Coventry
• On-site
• £21,805 pa
• Entry level
• Contract

Develops medium-voltage solid-state transformer cells for hyperscale AI data centres and net-zero grids, tackling high-frequency power conversion, compact magnetic links and electrical-thermal degradation under high-dv/dt stress. Combines multi-physics finite-element modelling in ANSYS/COMSOL with experimental validation in a high-voltage power electronics lab, culminating in a scaled hardware prototype.

ANSYS · COMSOL · FPGA +1