Semiconductor Jobs

Renesas Electronics · Edinburgh

Support silicon evaluation and applications engineering, working hands-on with real devices, evaluation boards and lab equipment. The intern collects and analyses measurement data, debugs device and board issues, and develops scripts for automated measurements alongside experienced engineers.

Renesas Electronics · Edinburgh

Owns verification of complex digital and mixed-signal ASIC designs, building SystemVerilog/UVM testbenches and running block-level to full-chip simulation, coverage and regression. Includes gate-level simulation with SDF timing annotation and mentoring junior engineers. Hybrid role with three set office days in Edinburgh.

Semtech · Bristol

Drive validation strategy for next-generation high-speed semiconductor devices, architecting end-to-end test solutions spanning software, hardware and documentation. Build Python or LabVIEW automation, take precision lab measurements at 10Gbit/s and above, and apply signal integrity expertise to schematic entry and PCB layout in Altium. Lead validation reviews and mentor engineers within a Bristol R&D team.

Octagon Group · Andover · £40,000 – £45,000 pa

Hands-on maintenance engineering role in an ISO 7 semiconductor assembly and test facility, covering scheduled preventative maintenance, fault investigation and repairs. Involves servicing HVAC, HEPA filtration and LEV systems, supporting utilities such as compressed air, nitrogen and power, and coordinating external service engineers alongside Production, Process Engineering and Quality.

Analog Devices · Edinburgh

Lead verification of complex mixed-signal ICs across the full development cycle, from concept and verification planning through implementation, execution and release. Develop UVM and formal testbench architectures, define coverage and closure metrics, debug gate-level simulations, and mentor junior engineers while leading IP or SoC verification efforts.

Analog Devices · Edinburgh

Join a Consumer Audio design team in Edinburgh to work on real mixed-signal IC development, from circuit architecture research and feasibility studies to transistor-level design, simulation and verification of analog blocks. You will build testbenches, analyse trade-offs around noise, distortion and power, and collaborate with layout engineers through physical implementation and design reviews.

Beautiful Recruitment · Hereford

Provide first-line engineering support for wafer fabrication and epitaxy process tools, handling fault diagnosis, repairs and preventative maintenance on lithography, etch, PVD, PECVD and MOVPE reactor systems. Work a continental 12-hour shift pattern in a safety-critical cleanroom, managing vacuum, pneumatic, mechanical, electrical and RF systems plus chemical and specialty gas supplies. Open to Armed Forces technical trades and aerospace/defence backgrounds, with training provided.

Platform Recruitment · Cambridge · £100,000 – £160,000 pa

Design and develop reusable FPGA modules in SystemVerilog for deployment across multiple next-generation products, with RTL verification and timing closure work. You'll write specifications, review code and documentation, and collaborate with hardware, software and mechanical engineers in a hybrid Cambridge team.

Lumai · Oxford

Own a Python-based performance and power modelling framework predicting how photonic AI hardware runs real inference workloads, giving architecture and compiler teams a shared source of truth for latency, throughput and power. Model compute engines, interconnect, memory and bridge interfaces, validate against RTL or emulation, and run benchmarks such as UL Procyon, Geekbench AI and LLMs.

Lumai · Oxford

Owns embedded software for a novel optical AI accelerator, writing Linux kernel and bare-metal device drivers, firmware for control processors, and deterministic RTOS control tasks. Leads board support package bring-up on new custom silicon revisions, debugging with JTAG, scopes and logic analysers, and sets the embedded team's coding standards and test methodology.

Reperio Human Capital · Cork, Ireland · £103,589 – £129,486 pa

Lead and grow a verification team while remaining hands-on with mixed-signal power ICs. You define verification strategy, methodology and sign-off criteria, architect UVM/SystemVerilog environments at block, subsystem and SoC level, and own verification plans, regressions and coverage closure. Works closely with design, firmware, applications and test teams, with three days a week on site in Cork.

Spectrum IT Recruitment · Southampton · £80,000 – £85,000 pa

Shapes complex high-performance products from requirements through implementation, spanning software, FPGA and ASIC. Defines hardware/software partitioning, interfaces and implementation strategies, evaluates trade-offs in performance, latency, resource usage and power, and builds architectural models with performance analysis. Works closely with software, algorithm, FPGA and ASIC engineers plus customers on feasibility and integration.

Platform Recruitment · Coventry · £40,000 – £60,000 pa

Work across the full FPGA design cycle, from requirements analysis and specification through RTL design, implementation and verification. Define module architectures, run synthesis and timing analysis, and integrate FPGAs into target hardware, using VHDL or Verilog and leading vendor tools alongside senior engineers and system architects.

Redline Group · Devizes · £80,000 – £100,000 pa

This role involves leading the end-to-end ASIC architecture for a novel probabilistic computing processor, spanning from algorithm and instruction set definition to tape-out and silicon bring-up. The architect will define system and microarchitecture specifications, perform HW/SW co-design, and build performance and functional models. The position is central to shaping next-generation computing technology in a high-impact, innovation-driven environment.

Amazon · Cambridge

Architect and implement SoC designs for Blink/Ring smart home cameras and doorbells, owning the flow from RTL delivery through synthesis, power analysis and timing closure. The role also involves defining microarchitecture specs, mentoring junior engineers, and evaluating emerging IP blocks in a vertically integrated environment spanning architectural modelling to post-silicon validation.