IonQ · 501–1000 people · Public
Senior FPGA Verification Engineer
- Oxford
- Hybrid
- Senior
Architect and maintain UVM/SystemVerilog verification environments for complex FPGA designs, defining verification plans with constrained-random testing and functional coverage. Build automated regression suites and CI pipelines, collaborating with RTL engineers to debug and ensure reliable quantum control systems.
SystemVerilog · UVM · Python