Semiconductor Jobs

• Edinburgh
• Senior · manages people
• Permanent

Lead the design and verification of CMOS analog blocks for custom mixed-signal ASICs, taking technical ownership of full-chip or major system-level blocks from specification through to production ramp. The role combines hands-on circuit design with mentoring a team of engineers, working alongside digital, layout, DFT and test teams, and driving silicon debug and characterisation.

Cadence · EDA

• Bristol
• Hybrid · 4 days in office
• Senior

Develop, deploy and optimise wafer and package-level test solutions on the Advantest V93000 platform, covering test development, characterisation, qualification support and production ramp-up. Work closely with design, product engineering and offshore OSAT partners across the full product lifecycle, with a focus on high-speed mixed-signal ICs, DFT and yield/test-time improvement.

Advantest V93000

• Edinburgh
• Hybrid
• Lead
• Permanent

Provide technical leadership for a global engineering compute and design-data-management environment, combining hands-on CAD work with infrastructure ownership. You will own Perforce Helix and IPLM methodologies, build Python and shell automation, and guide migration from legacy data platforms. The role spans Linux compute environments, EDA tool configuration, documentation and training across distributed semiconductor teams.

Perforce Helix · Methodics IPLM · Cadence Virtuoso +4

• Edinburgh
• Senior

Contribute to pre-silicon verification of analog and mixed-signal products, covering top-level DMS SV/UVM, gate-level simulation, and metric-driven AMS simulations. Bridge verification and validation environments to support post-silicon validation while establishing and improving verification flows and models for a global multi-disciplinary team.

Cadence Xcelium · Cadence IMC · Cadence Virtuoso +7

• Newbury
• On-site
• Entry level
• Internship

Join the CSS design verification team to validate IP and subsystem-level designs for high-performance semiconductor products. You will develop System Verilog/UVM testbenches, run simulations, debug failures, and track functional and assertion coverage alongside design and architecture engineers.

SystemVerilog · Verilog · UVM +7

• Bristol
• Remote
• Lead

Customer-facing technical strategist driving design wins for high-speed analog ICs (drivers, TIAs, copper redrivers) with Tier 1 hyperscalers and EMEA optical accounts. Leads co-development of 1.6T/3.2T interconnect, signal integrity and transceiver validation, while also supporting PON and Mobile Transport accounts and influencing product roadmaps.

IEEE 802.3 · OIF · ITU-T PON +7

• Swindon
• Hybrid
• Lead
• Permanent

Provide technical leadership for a global engineering compute and design-data-management environment, combining hands-on CAD work with Perforce Helix and IPLM-based data management. You will develop Linux-based engineering environments, Python and shell automation, project/workspace methodologies, and migration paths from legacy platforms, while supporting EDA tool integration and training engineering teams.

Perforce Helix · Methodics IPLM · Cadence Virtuoso +3

• Edinburgh
• Entry level
• Internship

Hands-on internship in a design verification team, validating IP and subsystem-level designs for high-performance semiconductor products. You will develop System Verilog/UVM testbenches, run simulations, debug failures, create directed and constrained-random tests, and track functional, code and assertion coverage while supporting regression automation with scripting.

SystemVerilog · Verilog · UVM +7

• Edinburgh
• Senior

Implements and verifies digital logic for mixed-signal SoCs used in high-performance power systems, covering RTL development, synthesis, static timing analysis and DFT insertion. Works with analog, firmware and validation teams on integration, silicon bring-up and lab debug, with scope to improve methodology and automation.

Genus · Innovus · Tempus +4

• Newbury
• Senior

Lead the architecture and transistor-level design of mixed-signal ICs such as ADCs, DACs, PLLs and SerDes PHY subsystems for advanced FinFET SoC products. The role sits in the Advanced Cores Group, combining architectural decision-making, design reviews, layout and test guidance with mentoring of junior engineers.

FinFET

• Edinburgh
• Hybrid
• Lead · manages people
• Permanent

Lead verification of complex mixed-signal ICs across the full development cycle, from concept and verification planning through implementation, execution and release. Develop UVM and formal testbench architectures, define coverage and closure metrics, debug gate-level simulations, and mentor junior engineers while leading IP or SoC verification efforts.

UVM · SystemVerilog · Makefile +7

• Edinburgh
• Hybrid · 3 days in office
• Senior
• Permanent

Owns verification of complex digital and mixed-signal ASIC designs, building SystemVerilog/UVM testbenches and running block-level to full-chip simulation, coverage and regression. Includes gate-level simulation with SDF timing annotation and mentoring junior engineers. Hybrid role with three set office days in Edinburgh.

Synopsys VCS · Cadence Xcelium · Tcl +4

• Hayes
• Senior

Field Application Engineer supporting regional accounts across the UK, working with Account Managers and Business Unit specialists to solve complex application-level problems and drive design wins. Involves building customer relationships, identifying new business opportunities, training customers and presenting at seminars, with around 10% travel.

• Newbury
• On-site
• Senior

Field Applications Engineer role focused on system-level engagement with Aerospace, Defense and Communications customers at ADI's Newbury Catalyst site. You will develop and execute pilot demos using evaluation boards, system platforms and COTS modules, write Python code to tailor solutions, and work on-site with customers customising radar, electronic warfare and sensing designs. Part of the wider European System Platforms team, feeding customer insights back into future ADI products.

MATLAB · Python · COTS Modules

• Edinburgh
• Lead · manages people

Hands-on principal-level role owning the design and development of signal processing and machine learning algorithms for power system monitoring, asset health and grid analytics. Work spans the full pipeline from modelling and simulation to deployment across edge-to-cloud and embedded platforms, collaborating with hardware, firmware and data teams and engaging utilities and grid equipment OEMs. Includes mentoring engineers with a pathway to broader technical leadership.

Python · MATLAB · Simulink