Semiconductor Jobs

• Bristol
• Hybrid · 4 days in office
• Senior

Drive validation strategy for next-generation high-speed semiconductor devices, architecting end-to-end test solutions spanning software, hardware and documentation. Build Python or LabVIEW automation, take precision lab measurements at 10Gbit/s and above, and apply signal integrity expertise to schematic entry and PCB layout in Altium. Lead validation reviews and mentor engineers within a Bristol R&D team.

Python · LabVIEW · Altium

• Bristol

Designs circuit solutions for AI processor systems and validation platforms, turning requirements into schematics, layout constraints and testable hardware. Owns boards from first schematic through bring-up, lab validation, debug and production transfer, working closely with silicon, architecture, firmware and PCB CAD teams.

Linux · Python · Bash +7

• Fareham
• £55,000 – £65,000 pa
• Senior

Lead algorithm development for RISC-V-based capacitive touch controllers, owning projects from problem definition and modelling through experimentation, optimisation and validation on real hardware. Work spans sensor physics, mixed-signal electronics and DSP, designing filtering, calibration and noise-rejection algorithms while mentoring junior colleagues.

MATLAB · Python · RISC-V +5

• Didcot
• Hybrid · 4 days in office
• £41,414 – £67,481 pa
• Senior
• Contract

Develop and debug HDL firmware for Xilinx FPGAs in Vivado, implementing full-cycle designs for magnet power supplies on the Diamond-II upgrade, including feedback control, filtering and interlock state machines. Work with ADCs, DACs, memory and microcontrollers, verifying designs via simulation and on-hardware testing, and collaborate with hardware and control engineers on Ethernet-based interfaces.

Xilinx · Vivado · MATLAB +7

• Bristol
• Senior

Hands-on role owning reliability of AI compute hardware across lab and data centre environments, leading operational, diagnostic and engineering support. You will diagnose failures in server blades, racks, power, thermal, network and BIOS/BMC systems, driving root cause analysis and improved hardware bring-up and validation practices.

BIOS · BMC

• Newport
• On-site
• £80 – £85 ph
• Senior

Deliver FPGA development work packages end to end, from requirements analysis and architectural design through VHDL implementation, simulation, verification and integration into target hardware. Work onsite in South Wales on complex hardware projects, reporting progress against cost, schedule and quality targets, with scope to lead and review engineering work.

Altera Quartus II · Mentor ModelSim · Microsemi Libero IDE +5

• United Kingdom
• On-site
• £500 – £1,000 pd
• Contract

Contract roles spanning embedded software, FPGA and electronics hardware engineering for a UK SME delivering complex systems in highly regulated, secure environments. Day-to-day work includes low-level C/C++ development, VHDL/Verilog FPGA design, digital and electronic hardware design, debugging, and lifecycle work from requirements through integration, verification and test alongside multidisciplinary teams.

Ethernet · TCP/IP · SPI +6

• Bristol
• Hybrid · 4 days in office
• Senior

Lead bench PVT characterization for high-speed optical and electrical signal integrity products, developing automated test environments and analyzing complex datasets. Work with an international team across the UK, Canada, US and Mexico, using Python automation and mentoring junior engineers in a lab-based NPI role.

Python

• Whiteley
• £50,000 – £80,000 pa
• Senior

Design and optimise capacitive sensing architectures, develop and verify RTL in Verilog/SystemVerilog, and write embedded C/C++ software for sensing and signal processing. Lead silicon bring-up, debugging and validation across analogue, digital and firmware domains, collaborating with global teams on HMI solutions.

Verilog · SystemVerilog · C/C++ +7

• Farnborough

Design, develop and test embedded software and firmware for specialist engineering applications, contributing across the full lifecycle from research and prototyping to validation and product development. Work within a multidisciplinary team spanning software, FPGA and hardware engineering, with opportunities to broaden expertise across FPGA, DSP, electronics and RF technologies.

Vivado · Vitis · ModelSim +3

• Edinburgh
• Hybrid · 3 days in office
• Senior
• Permanent

Owns verification of complex digital and mixed-signal ASIC designs, building SystemVerilog/UVM testbenches and running block-level to full-chip simulation, coverage and regression. Includes gate-level simulation with SDF timing annotation and mentoring junior engineers. Hybrid role with three set office days in Edinburgh.

Synopsys VCS · Cadence Xcelium · Tcl +4

• Oxford
• £80,000 – £120,000 pa
• Lead

Lead the architecture and full lifecycle delivery of high-throughput FPGA subsystems for next-generation medical device platforms, from requirements through RTL implementation, ASIC bring-up and lab validation. The role combines hands-on SystemVerilog/Verilog design using AMD/Xilinx toolchains with technical leadership, mentoring mid/senior engineers and championing CI/CD automation.

AMD · Xilinx · Vivado +3

• Darlington

Characterise and model compound semiconductor devices, developing compact models for GaN and GaAs technologies and running DC, pulsed I-V, noise and small/large-signal RF testing. You will build and validate MMIC Process Design Kits, support customer design queries and work with design engineers on new process development. Requires UK nationality and security clearance.

IC-CAP · ADS · Microwave Office +2

• Chelmsford

Hands-on role spanning clean-room and office work, owning verification and test across space and science imaging detector projects. You define test flows, commission and script EGSE/OGSE/MGSE equipment, run functional, electrical, mechanical and environmental campaigns to ECSS standards, and train operations staff. Works closely with project, product assurance and manufacturing teams.

MATLAB · Python · Microsoft Excel +6

• Swindon
• Hybrid
• Senior
• Permanent

Provides technical leadership for a global EDA/CAD compute and engineering infrastructure, spanning Linux environments, LSF batch compute, EDA license servers, Perforce and project/workspace provisioning. Combines hands-on Python and shell automation with architecture, monitoring and capacity planning, working across engineering, CAD and IT/IS teams to keep semiconductor development environments consistent and reliable worldwide.

LSF · Perforce Helix · IPLM +6