RTL Design Team Lead - FPGA / ASIC
Lead a hardware design team while remaining hands-on in RTL development for FPGA and ASIC platforms, delivering high-performance Layer 1 IP for advanced 5G and satellite communications systems. Translate system requirements into optimised digital designs, drive technical roadmaps, and collaborate with algorithm, software, and product teams. Focus on timing, throughput, power efficiency, and integration of AI tools into design workflows.