Semiconductor Jobs

• Edinburgh
• Entry level
• Internship

Hands-on internship in a design verification team, validating IP and subsystem-level designs for high-performance semiconductor products. You will develop System Verilog/UVM testbenches, run simulations, debug failures, create directed and constrained-random tests, and track functional, code and assertion coverage while supporting regression automation with scripting.

SystemVerilog · Verilog · UVM +7

• Edinburgh
• On-site
• Entry level
• Internship

Join a collaborative Edinburgh team developing low-power analog and power-management IP for highly integrated mixed-signal ICs. The intern contributes to architecture, transistor-level design, simulation and verification of DC/DC converter IP such as buck, boost and buck-boost topologies, including analog sub-circuits like error amplifiers, comparators and gate drivers. Work spans behavioural modelling, layout review and potentially laboratory silicon evaluation.

Cadence Virtuoso · Spectre · SIMPLIS +2

• London
• Hybrid
• Mid-level
• Permanent

Contribute to fundamental and applied AI research, generating ideas, designing experiments and translating them into scalable implementations. Work spans efficient training and inference, world models, reinforcement learning and life sciences, with a focus on hardware-aware algorithms and low-level performance optimisation in C++/CUDA/Triton. Collaborate with silicon and software engineers and publish at NeurIPS, ICML and ICLR.

PyTorch · JAX · CUDA +3

• Cambridge
• Hybrid
• Mid-level
• Permanent

Conducts AI/ML research at Graphcore, generating ideas, designing experiments and translating them into scalable implementations, with a focus on hardware-aware algorithms and performance optimisation. Works with researchers, silicon and software engineers, and publishes at conferences such as NeurIPS, ICML and ICLR. Requires strong Python/PyTorch or JAX skills plus lower-level C++/CUDA/Triton programming.

PyTorch · JAX · XLA +1

• London
• Hybrid
• Mid-level
• Permanent

Develops FPGA-based digital control hardware for next-generation photonic quantum computing systems, covering architecture, RTL design, simulation, synthesis, timing analysis and verification. Works in a multidisciplinary R&D team with electronics engineers, physicists and software developers on high-speed, low-latency control and signal processing, including ADC/DAC interfacing and hardware bring-up.

Xilinx Vivado · Intel Quartus · ADC +2

• Bristol
• Remote
• Lead

Customer-facing technical strategist driving design wins for high-speed analog ICs (drivers, TIAs, copper redrivers) with Tier 1 hyperscalers and EMEA optical accounts. Leads co-development of 1.6T/3.2T interconnect, signal integrity and transceiver validation, while also supporting PON and Mobile Transport accounts and influencing product roadmaps.

IEEE 802.3 · OIF · ITU-T PON +7