Semiconductor Jobs

• Bristol
• £45,000 pa
• Entry level
• Permanent

Two-year graduate programme spanning Hardware Design and Signal Integrity on the electronic systems behind AI compute platforms. You'll develop circuits, schematics and PCB layouts, or analyse PCIe, Ethernet and DDR interfaces using simulation tools like Mentor Expedition, Ansys HFSS and Keysight ADS, comparing models with lab measurements.

Mentor Expedition · Ansys HFSS · Keysight ADS +3

• Bristol

You will build and maintain test systems for AI hardware platforms, defining test methods, specifying equipment and automating checks for high-speed serial links, high-current power supplies and PCBA debug. Embedded in the Hardware Test team, you work closely with silicon, firmware and production groups, improving coverage and transferring robust solutions into production.

Ethernet · PCIe · Python +4

• Oxford
• Hybrid
• Junior
• Permanent

Builds firmware, peripheral drivers and RTOS-based control software for an optical AI accelerator, covering RTOS tasks and IPC, board support package bring-up, boot loaders and first-boot debugging on custom hardware. Works closely with a senior embedded engineer and hardware teams, writing unit and integration tests and maintaining embedded CI pipelines.

FreeRTOS · Zephyr · JTAG +7

• Cambridge
• Hybrid
• £35,000 – £45,000 pa
• Mid-level

Develops FPGA and embedded firmware for high-performance data acquisition and signal processing systems used in biomedical research. Writes VHDL for FPGA functionality and C for low-level hardware control, integrating and debugging digital electronics alongside hardware and software engineers. Offers real project ownership and a progression route to senior engineering roles.

AMD Vivado · Xilinx Vivado · Intel Quartus +5

• Didcot
• Hybrid · 4 days in office
• £41,000 – £67,000 pa
• Senior
• Contract

Develops, tests and optimises FPGA firmware in VHDL or Verilog for next-generation control systems and power electronics, including interfaces to ADCs, DACs, memory and microcontrollers. Involves simulation, verification, lab-based hardware debugging and collaboration with hardware, software and systems engineers. Senior applicants can lead development activities and mentor others.

Xilinx · LTspice · PSpice +6

• Oxford
• Hybrid
• Senior
• Permanent

Owns dense, high-layer-count PCB layout from schematic handoff to fabrication release, covering stackups, HDI structures, controlled-impedance routing, differential pairs and BGA breakout for large FPGAs and custom ASICs. Acts as the main technical contact with fabricators and assembly houses, and sets the footprint libraries, design rules and CAD standards the team works to.

Cadence Allegro · Altium · Gerber +7

• Fareham
• £33,000 – £38,000 pa
• Junior

Develop and debug embedded C firmware for microcontrollers, support capacitive sensing algorithm development, and use Python for modelling, simulation and data analysis. Work alongside software, hardware and applications engineering teams on new features, investigating performance issues across software and hardware.

Git · SVN · MATLAB +1

• Guildford
• On-site
• £40,000 – £46,000 pa
• Entry level

Join a multidisciplinary team building integrated software-hardware systems for defence and security, spanning low-power embedded devices to high-throughput server applications. You'll apply C/C++, FPGA, and electronics skills to complex projects combining custom hardware with innovative software, with labs and prototyping facilities on site.

FPGA · VHDL · PCB

• Edinburgh
• Senior · manages people
• Permanent

Define test strategies for mixed-signal ICs and develop software and hardware test solutions on ATE platforms such as Advantest V93K, Cohu DiamondX and Teradyne UltraFLEX. The role covers silicon characterisation, production testing, correlation and release at production facilities, plus leading the test development project and mentoring junior engineers.

Advantest V93K · Cohu DiamondX · Teradyne UltraFLEX +2

• Bristol
• £65,000 – £75,000 pa
• Senior

Designs RTL for next-generation communication systems, working on both FPGA and ASIC platforms using Verilog or SystemVerilog. The role sits within an expanding electronics manufacturer and calls for signal processing or digital communications knowledge plus scripting, typically in Python.

Verilog · SystemVerilog · Python

• Bristol
• Hybrid
• £80,000 – £900,000 pa
• Senior
• Permanent

Take technical ownership of FPGA and programmable logic design for advanced gimbal payload systems, covering video capture and processing, sensor and high-speed serial interfaces, and real-time pointing and stabilisation control. Lead RTL design, verification, synthesis and hardware bring-up, taking in-house boards from prototype to qualified production while mentoring other engineers.

Altium · Oscilloscopes · Logic Analysers +1

• Cambridge
• Hybrid · 3–4 days in office
• £75,000 – £85,000 pa
• Permanent

Own FPGA logic for controller boards at the heart of the company's hardware, covering design, verification and maintenance. Work is VHDL-based on Xilinx Artix-7 parts in Vivado, spanning state machines, I²C/SPI driver logic, self-checking test benches and hands-on lab bring-up. Sits at the discrete-logic and embedded-interfaces level rather than SoC development.

Xilinx Artix-7 · Vivado · SVN +2

• London
• Hybrid
• Mid-level
• Permanent

Develops FPGA-based digital control hardware for next-generation photonic quantum computing systems, covering architecture, RTL design, simulation, synthesis, timing analysis and verification. Works in a multidisciplinary R&D team with electronics engineers, physicists and software developers on high-speed, low-latency control and signal processing, including ADC/DAC interfacing and hardware bring-up.

Xilinx Vivado · Intel Quartus · ADC +2

• Edinburgh
• Hybrid · 3 days in office
• Senior
• Permanent

Owns verification of complex digital and mixed-signal ASIC designs, building SystemVerilog/UVM testbenches and running block-level to full-chip simulation, coverage and regression. Includes gate-level simulation with SDF timing annotation and mentoring junior engineers. Hybrid role with three set office days in Edinburgh.

Synopsys VCS · Cadence Xcelium · Tcl +4

• Southampton
• Hybrid · 3 days in office
• £70,000 – £80,000 pa
• Senior

Works across the full FPGA development lifecycle, from architecture and VHDL/Verilog design through simulation, verification, timing closure and lab-based hardware testing. Involves high-speed digital interfaces, DSP and SoC platforms such as Xilinx Zynq, within a multidisciplinary engineering team. Open to mid and senior level engineers.

MATLAB · Simulink · Xilinx Zynq +7