Semiconductor Jobs

• Edinburgh
• On-site
• Entry level
• Internship

Join a collaborative Edinburgh team developing low-power analog and power-management IP for highly integrated mixed-signal ICs. The intern contributes to architecture, transistor-level design, simulation and verification of DC/DC converter IP such as buck, boost and buck-boost topologies, including analog sub-circuits like error amplifiers, comparators and gate drivers. Work spans behavioural modelling, layout review and potentially laboratory silicon evaluation.

Cadence Virtuoso · Spectre · SIMPLIS +2

• Sevenoaks
• Lead

Leads the design and development of high-speed analog ICs from concept through to volume production, acting as technical authority on circuit architecture and chip subsystems. Works across Stansted and Ottawa design centres on transimpedance amplifiers and laser drivers for datacentres, 5G and fibre-to-the-home, mentoring junior engineers and collaborating with cross-functional teams.

Cadence · Verilog-AMS · SystemVerilog +6

• Bristol
• Hybrid · 4 days in office
• Lead · manages people

Lead a Bristol team of analog IC design engineers, spanning associate to senior level, with direct oversight of performance, development and recruitment. The role is hands-on, guiding complex design work while managing project schedules, budgets and cross-functional priorities for optical communications ICs such as laser drivers, TIAs and transceivers.

SiGe BiCMOS · CMOS · GaAs +2

• Edinburgh
• On-site
• Entry level
• Permanent

Support the design and verification of analog integrated circuit blocks, from transistor-level schematic capture and simulation through layout review and debug. Work alongside experienced engineers on real silicon projects, documenting and presenting findings to the team.

• Edinburgh
• Senior
• Permanent

Design and verify CMOS analog blocks such as amplifiers, oscillators, LDOs, comparators and reference/biasing circuits for custom ASICs, balancing performance, area, power and timescale. The role carries technical leadership of sub-systems from specification through to production ramp, guiding layout, DFT and test engineers, driving silicon debug and lab evaluation, and mentoring less experienced team members.

Cadence · EDA Design Tools

• Newbury
• Entry level
• Internship

Contribute to the design, verification, layout and evaluation of analog and mixed-signal circuits for high-precision 16-20 bit, >10MSps SAR A/D converters. Work alongside the High-Speed SAR ADC Group in Newbury, gaining hands-on IC design experience with MATLAB, Verilog and LabVIEW. Internships run 3 to 12 months.

MATLAB · Verilog · LabVIEW

• Newbury
• Senior

Designs multi-channel digital receivers and transmitters for phased-array, radar, electronic warfare and satellite communication markets, developing RF converter-centric hardware and software from concept to productization. Analyses signal chains using RF cascade concepts and guides customers through system integration, troubleshooting and testing.

MATLAB · Python · C/C++

• Edinburgh
• Entry level
• Internship

Placement students work alongside engineering teams on real, challenging assignments, contributing to product development across electronics, software and computer science. Interns are paired with experienced mentors and treated as extended interview candidates for future full-time roles, with work spanning IoT, automotive radar, healthcare and 5G systems.

5G · IoT

• Swindon
• Senior
• Permanent

Serve as technical lead for analog and power solutions, supporting customer design engagements from concept to production. Involves power tree design, device selection, schematic and layout reviews, hands-on debug, and delivering field feedback to product divisions. Works closely with sales and travels regularly to customer premises across the UK and Ireland.

PMICs · DC/DC · GaN +7

• Bourne End
• Senior
• Permanent

Serve as technical lead for analog and power solutions, supporting UK and Ireland customers from pre-design through production. Drive design-ins and design-wins via architecture development, schematic and layout reviews, bench validation, and hands-on debug across PMICs, DC/DC, GaN, and signal chain. Act as the field voice back to product divisions while working within the sales team.

PMICs · DC/DC · GaN +7

• Bristol
• Hybrid · 4 days in office
• Senior

Architect test strategies for high-speed mixed-signal and RF SiGe products, from first silicon to mass production, covering 200Gbps+ SerDes, CDRs and signal conditioning. Sets DFT and testability standards, builds reusable test IP, and leads NPI transfers to high-volume OSATs while mentoring engineers.

Advantest V93000 · SmarTest 7/8 · C/C++ +7

• Sevenoaks
• Hybrid · 4 days in office
• CA$95,000 – CA$122,000 pa
• Senior

Owns new product introduction for high-speed analog and mixed-signal ICs, from concept through volume manufacturing and end-of-life. Defines DfT/DfM requirements, drives ATE test program development, PVT characterisation, ATE-to-bench correlation, yield analysis and DOE-based optimisation. Works cross-functionally with design, test, quality and operations, and mentors junior engineers.

Excel · JMP · Galaxy +6

• Bristol
• Senior

Owns new product introduction for high-speed analog and mixed-signal ICs, from concept through volume manufacturing. Defines DfT/DfM requirements, runs ATE-to-bench correlation and PVT characterization, and drives yield, test-time and cost optimization with design, test and foundry teams. Also mentors junior engineers and leads failure analysis and corrective actions.

Excel · JMP · Galaxy +6

• Edinburgh
• Entry level
• Internship

Hands-on internship working on meaningful engineering projects alongside a team of experts, with collaboration across the business and access to lunch-and-learn sessions and social events. Interns are developed with the aim of being first in line for full-time roles, and the programme sits within a global semiconductor leader working across analog, digital, AI and software technologies.