Semiconductor Jobs

• Bristol
• £2,500 pm
• Entry level
• Internship

A 12-week summer internship in the Product Test and Diagnosis team within Manufacturing Operations, working hands-on with advanced AI hardware across silicon, boards, server blades or rack-scale systems. You'll develop automated test solutions, run system-level tests and analyse results, connecting manufacturing test to design, validation and performance.

Python · Linux · Bash +2

• Bristol
• Senior

Leading role supporting NPI development and volume production of complex AI hardware, providing DfM feedback on PCB and system design and working closely with contract manufacturers. Drives yield improvement, analyses production data and resolves L6 manufacturing issues, with travel to Taiwan to work alongside suppliers.

JMP · SQL · Python +2

• Cambridge

Hands-on development of kernel generation and computational graph optimizations for next-generation NVIDIA GPUs, solving complex compilation problems for AI inference and training workloads. The role involves co-designing future silicon with software, hardware and research teams, and optimizing datacenter-scale AI deployments using MLIR, C/C++ and Python.

MLIR · GPU · CPU +1

• Coventry
• On-site
• £21,805 pa
• Entry level
• Contract

Develops medium-voltage solid-state transformer cells for hyperscale AI data centres and net-zero grids, tackling high-frequency power conversion, compact magnetic links and electrical-thermal degradation under high-dv/dt stress. Combines multi-physics finite-element modelling in ANSYS/COMSOL with experimental validation in a high-voltage power electronics lab, culminating in a scaled hardware prototype.

ANSYS · COMSOL · FPGA +1

• Manchester
• £21,805 pa
• Entry level
• Contract

A 3.5-year funded PhD designing a Smart Network-on-Chip, an asynchronous communication fabric with intelligence built into its microarchitecture, to manage congestion in 2.5D chiplet systems. The work replaces static routing heuristics with data-driven, learning-based policies, building on an existing RTL-verified asynchronous NoC IP, with possible directions in lightweight inference engines and distributed adaptive traffic management.

CPUs · GPUs · AI Accelerators +5

• Newcastle upon Tyne
• Lead

Develops and maintains a C++ codebase for next-generation EDA tools, focusing on computational geometry, geometry manipulation and algorithmic complexity for sub-20nm IC design. Involves writing design, function and test specifications, interfacing with build and regression systems, and collaborating with a global cross-functional team.

Qt · Linux · Unix

• Edinburgh
• Senior

Contribute to pre-silicon verification of analog and mixed-signal products, covering top-level DMS SV/UVM, gate-level simulation, and metric-driven AMS simulations. Bridge verification and validation environments to support post-silicon validation while establishing and improving verification flows and models for a global multi-disciplinary team.

Cadence Xcelium · Cadence IMC · Cadence Virtuoso +7

• Edinburgh
• Hybrid
• Lead · manages people
• Permanent

Lead verification of complex mixed-signal ICs across the full development cycle, from concept and verification planning through implementation, execution and release. Develop UVM and formal testbench architectures, define coverage and closure metrics, debug gate-level simulations, and mentor junior engineers while leading IP or SoC verification efforts.

UVM · SystemVerilog · Makefile +7

• Northamptonshire
• On-site
• Shift work

Provide first-line engineering support for wafer fabrication and epitaxy process tools, handling fault diagnosis, repairs and preventative maintenance on lithography, etch, PVD, PECVD and MOVPE reactor systems. Work a continental 12-hour shift pattern in a safety-critical cleanroom, managing vacuum, pneumatic, mechanical, electrical and RF systems plus chemical and specialty gas supplies. Open to Armed Forces technical trades and aerospace/defence backgrounds, with training provided.

Lithography · Etch · PVD +6

• Oxford
• Hybrid
• Senior

Lead validation and characterisation of analogue and mixed-signal ASICs for trapped-ion quantum processors, from test planning and platform development through first-silicon bring-up, debug and system integration. The role spans room-temperature and cryogenic (around 4 K) measurements on packaged parts, chip-on-board assemblies and bare die, with heavy Python automation and test PCB work.

Python · Git · SPI +7

• Bristol
• £2,500 pm
• Entry level
• Internship

Join one of four specialist silicon teams—logical design, verification, physical design or design for test—contributing to real AI chip development over a 12-week summer placement. You'll work with industry-standard EDA tools on tasks such as RTL design, SOC integration, verification methods or physical implementation, with support from experienced engineers.

EDA Tools