Semiconductor Jobs in Cambridge

• Cambridge
• On-site
• Senior
• Permanent

Design and layout of GaN power ICs using EDA tools, covering schematic capture, analog simulation, chip layout review, PEX and PLS. The role also involves wafer-level and packaged device testing, SPICE model development, and supporting patent and IP management within a growing R&D engineering team.

EDA Tools · SPICE · GaN

• Cambridge
• On-site
• Senior
• Permanent

Define and architect test hardware for GaN power devices and ICs, covering fixtures, sockets, probing, switching and multi-site parallel setups for static, dynamic and mixed-signal measurements. Lead test hardware workstreams from concept to release, write specifications, review designs, and mentor engineers while shaping the test equipment roadmap.

HTRB · HTOL

• Cambridge
• Mid-level

Designs and develops FPGA firmware for defence technologies spanning communications, sensors and detection systems, working within a small multidisciplinary engineering team. Uses VHDL or Verilog and collaborates with internal teams and external groups, with security clearance required and room to grow as the company expands.

• Cambridge
• On-site
• £45,000 – £55,000 pa
• Mid-level

Own significant blocks of RTL from specification through implementation, verification and into working hardware, focused on physical layer design in the communications space. Work alongside senior and principal engineers on digital RF and fixed-point DSP, with hands-on lab time on AMD/Xilinx FPGA platforms. A new role in a small, established team with low attrition.

AMD · Xilinx · MATLAB

• Cambridge
• Hybrid
• £60,000 – £75,000 pa
• Senior

Lead high-speed board-level electronics and FPGA development for a technology consultancy, delivering client projects across varied markets. Also contribute to internal R&D, building prototypes and demonstration platforms, with opportunities for technical leadership and mentoring.

DDR4 · QSPI · PCIe +4

• Cambridge
• £60,000 – £90,000 pa
• Senior

Own the full product lifecycle for complex instruments used in defence and security, from concept through to prototype production. Day-to-day work centres on HDL design with VHDL or SystemVerilog, using toolchains such as Vivado or Quartus, running simulations and testbenches, and performing hardware-level debugging. Requires UK security clearance.

Vivado · Quartus

• Cambridge
• Hybrid
• £100,000 – £160,000 pa
• Senior

Design and develop reusable FPGA modules in SystemVerilog for deployment across multiple next-generation products, with RTL verification and timing closure work. You'll write specifications, review code and documentation, and collaborate with hardware, software and mechanical engineers in a hybrid Cambridge team.

SystemVerilog · Python · Cocotb +4

• Cambridge
• Hybrid · 3–4 days in office
• £75,000 – £85,000 pa
• Permanent

Own FPGA logic for controller boards at the heart of the company's hardware, covering design, verification and maintenance. Work is VHDL-based on Xilinx Artix-7 parts in Vivado, spanning state machines, I²C/SPI driver logic, self-checking test benches and hands-on lab bring-up. Sits at the discrete-logic and embedded-interfaces level rather than SoC development.

Xilinx Artix-7 · Vivado · SVN +2

• Cambridge
• £100,000 – £180,000 pa
• Senior

Owns all aspects of FPGA system design, architecting and implementing RTL on high-end Xilinx/Intel devices for ultra-low-latency infrastructure. Leads micro-architecture definition, verification environments and timing closure while mentoring the FPGA team and collaborating with firmware, software and infrastructure engineers on full-stack optimisation.

Xilinx · Intel · Vivado +2

• Cambridge
• Hybrid
• Mid-level

Design and implement FPGA-based SoC systems for cutting-edge thermal imaging and augmented reality products, contributing reusable modules to a shared library. Work within a multidisciplinary hardware, software and mechanical team, using VHDL, Verilog, SystemVerilog verification, Python and low-power design techniques.

FPGA · VHDL · Verilog +2

• Cambridge
• Hybrid
• Mid-level

Design and implement FPGA-based SoC systems for cutting-edge thermal imaging and augmented reality products, contributing reusable modules to a shared library. Work in a multidisciplinary team of hardware, software and mechanical engineers, using VHDL, Verilog, SystemVerilog and Python, with a focus on low-power design and timing constraints.

FPGA · VHDL · Verilog +2

• Cambridge
• On-site
• Mid-level
• Permanent

Designs and develops RF front-end circuits and functional blocks, integrating them into low-loss, high-performance multi-chip modules. Works closely with IC designers, systems, algorithm and software teams to optimise module performance and define test plans in a fast-moving fabless semiconductor start-up.

• Cambridge
• On-site
• Lead
• Permanent

Hands-on technical lead for RF subsystem design, simulation and validation, covering circuits such as LNAs, PAs, filters and duplexers. Owns performance, quality and delivery against system architecture, runs design reviews and verification (S-parameters, NF, phase noise, EVM, ACPR), and mentors RF engineers while working with the System Architect and manufacturing teams.

• Cambridge
• Hybrid
• Mid-level
• Permanent

Conducts AI/ML research at Graphcore, generating ideas, designing experiments and translating them into scalable implementations, with a focus on hardware-aware algorithms and performance optimisation. Works with researchers, silicon and software engineers, and publishes at conferences such as NeurIPS, ICML and ICLR. Requires strong Python/PyTorch or JAX skills plus lower-level C++/CUDA/Triton programming.

PyTorch · JAX · XLA +1

• Cambridge
• Lead · manages people

Technical leadership role owning product-level characterisation strategy, translating requirements and risks into proportionate test coverage, analysis and reporting. Leads a small team developing automated volume test solutions while hands-on with wafer-level ATE characterisation, RF/analogue test design and large-dataset analysis, presenting findings to stakeholders from project inception through production transfer.

Python · LabVIEW · C# +2