Semiconductor Jobs

Renesas Electronics · Swindon

Provides technical leadership for a global EDA/CAD compute and engineering infrastructure, spanning Linux environments, LSF batch compute, EDA license servers, Perforce and project/workspace provisioning. Combines hands-on Python and shell automation with architecture, monitoring and capacity planning, working across engineering, CAD and IT/IS teams to keep semiconductor development environments consistent and reliable worldwide.

Renesas Electronics · Edinburgh

Provides technical leadership for a global EDA/CAD compute and engineering infrastructure, spanning Linux environments, LSF batch compute, EDA license servers, Perforce and project/workspace provisioning. Combines hands-on engineering with architecture and operational ownership, building Python and shell automation, monitoring dashboards and capacity planning. Works across engineering, CAD and IT/IS teams to keep environments scalable and globally consistent for semiconductor development.

Lumai · Oxford

Owns dense, high-layer-count PCB layout from schematic handoff to fabrication release, covering stackups, HDI structures, controlled-impedance routing, differential pairs and BGA breakout for large FPGAs and custom ASICs. Acts as the main technical contact with fabricators and assembly houses, and sets the footprint libraries, design rules and CAD standards the wider team works to.

Lumai · Oxford

Owns signal and power integrity across high-speed boards and packages, running pre-layout channel studies, post-layout SI analysis with IBIS-AMI models, and PDN impedance and DC drop work for high-current ASIC and FPGA rails. Channels span chip, package, interposer, board and optical engine, with heavy bench correlation using VNAs, TDRs and oscilloscopes to feed design rules.

Reperio Human Capital · Cork, Ireland · £86,324 – £103,589 pa

Own verification of mixed-signal ICs from test planning through final sign-off, building and maintaining UVM testbenches, coverage models and regression suites. Work closely with analog and digital design teams to catch issues early, track coverage closure, and help shape the team's verification approach while supporting other engineers.

Teledyne FLIR · Wilsonville, United States

This HR Business Partner role involves providing strategic people leadership to a major division within Teledyne FLIR's Defense business. The individual will partner with senior leaders globally to drive organizational effectiveness, talent development, and change management, using data-driven insights and AI-enabled analytics. The role requires proactive workforce planning, fostering inclusive culture, and supporting complex employee relations across multiple countries.

Copello · Bristol · £80,000 – £900,000 pa

Take technical ownership of FPGA and programmable logic design for advanced gimbal payload systems, covering video capture and processing, sensor and high-speed serial interfaces, and real-time pointing and stabilisation control. Lead RTL design, verification, synthesis and hardware bring-up, taking in-house boards from prototype to qualified production while mentoring other engineers.

Lumai · Oxford

Own a Python-based performance and power modelling framework predicting how photonic AI hardware runs real inference workloads, giving architecture and compiler teams a shared source of truth for latency, throughput and power. Model compute engines, interconnect, memory and bridge interfaces, validate against RTL or emulation, and run benchmarks such as UL Procyon, Geekbench AI and LLMs.

Lumai · Oxford

Owns embedded software for a novel optical AI accelerator, writing Linux kernel and bare-metal device drivers, firmware for control processors, and deterministic RTOS control tasks. Leads board support package bring-up on new custom silicon revisions, debugging with JTAG, scopes and logic analysers, and sets the embedded team's coding standards and test methodology.

Renesas Electronics · Edinburgh

Owns verification of complex digital and mixed-signal ASIC designs, building SystemVerilog/UVM testbenches and running block-level to full-chip simulation, coverage and regression. Includes gate-level simulation with SDF timing annotation and mentoring junior engineers. Hybrid role with three set office days in Edinburgh.