Semiconductor Jobs

Cambridge GaN Devices · Cambridge

Design and layout of GaN power ICs using EDA tools, covering schematic capture, analog simulation, chip layout review, PEX and PLS. The role also involves wafer-level and packaged device testing, SPICE model development, and supporting patent and IP management within a growing R&D engineering team.

Cambridge GaN Devices · Cambridge

Define and architect test hardware for GaN power devices and ICs, covering fixtures, sockets, probing, switching and multi-site parallel setups for static, dynamic and mixed-signal measurements. Lead test hardware workstreams from concept to release, write specifications, review designs, and mentor engineers while shaping the test equipment roadmap.

NVIDIA · Bristol

Lead security research, architecture and implementation for next-generation networking products, taking a hands-on role defining hardware and software security solutions. Work across teams and with external partners on IO interfaces, boot architecture, RISC-V, root-of-trust and secure platforms, guiding open-source implementation and customer threat resolution.

NVIDIA · Belfast

Lead security research, architecture and implementation for next-generation networking products, taking a hands-on role defining hardware and software security solutions. Work across internal teams and external partners on IO interfaces, boot architecture, RISC-V and root-of-trust, with architectural modelling and validation. Requires deep embedded and low-level firmware expertise.

Avanti Recruitment · ELY · £50,000 – £65,000 pa

Hands-on ownership of FPGA architecture for advanced sensing and Edge-AI products, spanning high-speed data acquisition, SoC-FPGA integration, real-time DSP and future CNN acceleration. Day-to-day work covers VHDL/Verilog/SystemVerilog RTL, ADC and LVDS acquisition, DMA, AXI and PS/PL integration, DDR streaming pipelines, timing closure and CDC, plus hardware bring-up and Embedded Linux/PetaLinux integration.

eFinancialCareers · London

Designs and operates ultra-low-latency trading systems at global scale, working across the latency-critical stack from kernel-level tuning and network optimisation to highly efficient C++ components. Collaborates closely with FPGA, hardware and infrastructure engineers on end-to-end architectures where every nanosecond counts.