Semiconductor Jobs

Renesas Electronics · Swindon

Provide technical leadership for a global engineering compute and design-data-management environment, combining hands-on CAD work with Perforce Helix and IPLM-based data management. You will develop Linux-based engineering environments, Python and shell automation, project/workspace methodologies, and migration paths from legacy platforms, while supporting EDA tool integration and training engineering teams.

Pragmatic Semiconductor · Durham

Owns metal-oxide PVD process development, qualification and sustaining on 300mm production tools, defining process windows and driving SPC, Cpk and root-cause investigations for yield-limiting film issues. Combines deep technical leadership of reactive sputtering with line management of a small deposition team, partnering with equipment, integration and reliability engineers.

Pragmatic Semiconductor · Stockton-on-Tees

Lead the technical development of FlexIC wafer-level packaging, chip-scale packaging, die attachment and system-in-package integration, setting technical direction and selecting materials, processes and partners. Drive the internal roadmap with Product Management, Engineering and Operations, validating scalable processes and transferring them to production teams. A newly created principal-level role spanning R&D, reliability qualification and external development partners.

Eclectic Recruitment · Stevenage · £55,000 – £65,000 pa

Lead high-speed digital electronics design across the full product lifecycle, developing MPSoC FPGA, DDR, Flash memory and high-speed serial interconnect solutions for software-defined radio, radar signal processing and sensor fusion. Work alongside Systems, Software, Firmware, Mechanical and Production teams on optimised hardware architectures, supporting board-level testing and debugging while progressing toward technical leadership.

Eclectic Recruitment · Stevenage · £70,000 – £85,000 pa

Lead a team of FPGA and digital design engineers while providing hands-on technical direction across FPGA architecture, RTL design, simulation, synthesis, timing closure and hardware validation. Own project execution including planning, estimation, scheduling and risk management, and work with Systems, Software, Hardware and Verification teams to deliver integrated solutions from concept through to production.

Lumai · Oxford

Builds firmware, peripheral drivers and RTOS-based control software for an optical AI accelerator, covering RTOS tasks and IPC, board support package bring-up, boot loaders and first-boot debugging on custom hardware. Works closely with a senior embedded engineer and hardware teams, writing unit and integration tests and maintaining embedded CI pipelines.

Teledyne FLIR · UK - Lincoln

Drive value stream and production method improvements to boost throughput and manufacturing capacity, support product ramp-ups and New Product Introduction, and improve manufacturing and test processes to raise yield and cut costs. Lead root cause investigations and corrective actions, and identify automation and tooling opportunities for future growth.

Cadence · Edinburgh

Develops verification and emulation environments for complex Chiplet designs, building UVM-SV scoreboards, functional coverage, and SystemVerilog assertions for formal and simulation. Integrates Cadence VIP and accelerated VIP, manages vPlans in vManager, and maintains automated regression environments using Jenkins and GIT within an experienced Chiplet team.

KBM Resourcing · Germany

Design and verify FPGA solutions using VHDL/Verilog for high-integrity aerospace and defence systems. Work within a multidisciplinary team to implement real-time, embedded FPGA functionality, ensuring robust integration and traceability across the development lifecycle.

Redline Group · Glasgow · £50,000 – £65,000 pa

Lead Electronics Engineer - East SussexDo you strive to be part of an organisation that develops cutting edge technologies for companies such as Samsung and Intel?If so I'd like to speak with you!A highly exciting Lead Electronics Engineer job has...

Semtech · Sevenoaks

Leads the design and development of high-speed analog ICs from concept through to volume production, acting as technical authority on circuit architecture and chip subsystems. Works across Stansted and Ottawa design centres on transimpedance amplifiers and laser drivers for datacentres, 5G and fibre-to-the-home, mentoring junior engineers and collaborating with cross-functional teams.

Semtech · Sevenoaks

Leads a multidisciplinary team of analog circuit and layout engineers across multiple high-speed IC product lines, owning the full NPI lifecycle from product definition to volume production. Drives tape-out, qualification, post-silicon bring-up and performance optimisation for TIAs and laser driver ICs up to 200G, working with teams in Stansted and Ottawa.

Jonathan Lee Recruitment · Maidenhead

Lead the architecture, design, implementation, integration and verification of FPGA-based firmware for high-assurance defence and cyber systems, using VHDL and structured V-model methodologies. Chair design reviews, translate ambiguous requirements into verifiable specifications, and mentor firmware engineers while working with protocols such as UART, SPI, I2C and TCP/IP. Based onsite in Maidenhead and requires security clearance eligibility.

Analog Devices · Edinburgh

Hands-on principal-level role owning the design and development of signal processing and machine learning algorithms for power system monitoring, asset health and grid analytics. Work spans the full pipeline from modelling and simulation to deployment across edge-to-cloud and embedded platforms, collaborating with hardware, firmware and data teams and engaging utilities and grid equipment OEMs. Includes mentoring engineers with a pathway to broader technical leadership.

Analog Devices · Edinburgh

Lead verification of complex mixed-signal ICs across the full development cycle, from concept and verification planning through implementation, execution and release. Develop UVM and formal testbench architectures, define coverage and closure metrics, debug gate-level simulations, and mentor junior engineers while leading IP or SoC verification efforts.