Hire by role

Hire verification engineers in the UK

What verification engineers are paid, what to name in the advert, and who you are up against — from the adverts on Semiconductor Jobs, not a survey. Looking for the roles themselves? See Verification Engineer jobs.

What you will pay

£67k to £85k, most around £85k

The range employers advertised for verification engineers on Semiconductor Jobs over the last 12 months, base salary only, across 3 priced adverts. Adverts that state a salary get more applications than those that hide it, and a figure at or above the midpoint is the single cheapest thing you can do for the response.

Remote or anchored

A fully remote role draws the whole country and can pay a little under the London figure; an anchored one competes locally and cannot.
Greenfield or inherited

Building from nothing is worth more to the right person than running what exists, and they will ask which it is.
Someone senior to learn from

A strong lead in the team is worth thousands on the offer; without one, expect to pay for that experience directly.

Who you are competing with

Hiring verification engineers on Semiconductor Jobs right now

IonQ 1

Three live adverts for the role, as candidates see them. How rivals pitch it is worth a look before you write yours.

Dabster Systems Ireland Limited

Design verification Engineer

Bristol
Remote
£50 – £60 ph
Senior

Verification of a next-generation multi-die SoC, covering subsystem- and SoC-level functional verification with SystemVerilog/UVM and processor-driven C test programs on embedded cores. Involves adapting existing UVM environments, debugging RTL simulation failures, running regressions and driving functional coverage closure, with scripting in Python, Perl or shell.

SystemVerilog · UVM · ARM +3

2 days ago

Dabster Systems Ireland Limited

SoC Design Verification Engineer

United Kingdom
£300 – £600 pd

Hands-on verification role covering subsystem and SoC functional verification, reusing and enhancing System Verilog/UVM testbenches, and developing processor-based C tests. The engineer runs regressions, debugs complex RTL simulation failures with waveform tools, and drives functional coverage closure while collaborating on verification planning.

SystemVerilog · UVM · Python +2

Last week

Graphcore

Silicon Verification Engineer - Multiple Levels

Bristol

Owns verification of complex AI compute silicon, ensuring RTL matches architecture specifications. Plans verification, defines coverage, generates tests, diagnoses failures and improves shared infrastructure, working closely with Architecture, Logical Design and Physical Design teams across multiple UK sites.

UVM · SVA · Git +2